cd7a70f487
This provides stack guards with checking and common entry into postcar. The code in cpu/intel/car/romstage.c is candidate for becoming architectural so function prototype is moved to <arch/romstage.h>. Change-Id: I4c5a9789e7cf3f7f49a4a33e21dac894320a9639 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34893 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
68 lines
2.0 KiB
C
68 lines
2.0 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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// Use simple device model for this file even in ramstage
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#define __SIMPLE_DEVICE__
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#include <arch/romstage.h>
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#include <console/console.h>
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#include <commonlib/helpers.h>
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#include <cpu/x86/mtrr.h>
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#include <device/pci_ops.h>
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#include <cbmem.h>
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#include <stage_cache.h>
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#include "haswell.h"
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static uintptr_t smm_region_start(void)
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{
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/*
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* Base of TSEG is top of usable DRAM below 4GiB. The register has
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* 1 MiB alignment.
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*/
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uintptr_t tom = pci_read_config32(PCI_DEV(0,0,0), TSEG);
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return tom & ~((1 << 20) - 1);
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}
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void *cbmem_top(void)
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{
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return (void *)smm_region_start();
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}
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/* Region of SMM space is reserved for multipurpose use. It falls below
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* the IED region and above the SMM handler. */
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#define RESERVED_SMM_OFFSET \
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(CONFIG_SMM_TSEG_SIZE - CONFIG_IED_REGION_SIZE - CONFIG_SMM_RESERVED_SIZE)
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void stage_cache_external_region(void **base, size_t *size)
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{
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/* The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET.
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* The top of RAM is defined to be the TSEG base address. */
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*size = CONFIG_SMM_RESERVED_SIZE;
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*base = (void *)((uint32_t)cbmem_top() + RESERVED_SMM_OFFSET);
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}
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void fill_postcar_frame(struct postcar_frame *pcf)
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{
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uintptr_t top_of_ram;
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/* Cache at least 8 MiB below the top of ram, and at most 8 MiB
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* above top of the ram. This satisfies MTRR alignment requirement
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* with different TSEG size configurations.
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*/
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top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB);
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postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB,
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MTRR_TYPE_WRBACK);
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}
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