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Eric Lai ce66f34372 mb/google/brya: Initiate device tree 
Initiate device tree based on latest schematic.

BUG=b:174266035
TEST=Build Test

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ia94119cb6d7eff6ea13c7d6a7dfd6ce891f706fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-04 21:10:31 +00:00
..
acpi
cbfs: Simplify load/map API names, remove type arguments
2020-12-02 22:13:17 +00:00
arch
x86: Put bootblock startup code into .text._start section
2020-12-03 00:10:34 +00:00
commonlib
cbfs: mcache: Fix end-of-cache check
2020-12-03 21:21:11 +00:00
console
lib/trace: Remove TRACE support
2020-12-02 23:35:58 +00:00
cpu
cpu/x86/smm_module_loaderv2: Fix compiling for x86_64
2020-12-04 17:20:30 +00:00
device
device: Drop unused HyperTransport code
2020-11-25 09:11:46 +00:00
drivers
drivers/intel/fsp2_0: FSP-T requires NO_CBFS_MCACHE
2020-12-04 11:00:45 +00:00
ec
src: Remove redundant use of ACPI offset(0)
2020-12-03 00:05:52 +00:00
include
cpu/x86/smm_module_loaderv2: Fix compiling for x86_64
2020-12-04 17:20:30 +00:00
lib
cbfs: Add verification for RO CBFS metadata hash
2020-12-03 00:11:08 +00:00
mainboard
mb/google/brya: Initiate device tree
2020-12-04 21:10:31 +00:00
northbridge
cbfs: Introduce cbfs_ro_map() and cbfs_ro_load()
2020-12-03 00:00:19 +00:00
security
cbfs: Add verification for RO CBFS metadata hash
2020-12-03 00:11:08 +00:00
soc
soc/intel/alderlake: Align chipset.cb with pci_devs.h
2020-12-04 21:10:19 +00:00
southbridge
cpu/qemu-x86: Add the option to have no SMM
2020-12-04 11:11:17 +00:00
superio
src: Remove redundant use of ACPI offset(0)
2020-12-03 00:05:52 +00:00
vendorcode
src: Remove redundant use of ACPI offset(0)
2020-12-03 00:05:52 +00:00
Kconfig
lib/trace: Remove TRACE support
2020-12-02 23:35:58 +00:00