cefee5e40f
The Intel Quark SoC does have a LAPIC on its x86 CPU core, so we should select CPU_X86_LAPIC. This will additionally include the Makefile from cpu/x86/lapic. Since none of AP_IN_SIPI_WAIT, LEGACY_SMP_INIT and UDELAY_LAPIC gets selected, only the boot_cpu.c and lapic.c targets will be added to the build. Since SMP isn't set, adding the boot_cpu.c target won't change the resulting binary of a timeless build, since the only function inside will be removed by the compiler's pre-processor in the !SMP case. So the only thing that will change the resulting binary is the addition of the lapic.c target. From this target only the function cpu_get_lapic_addr will be used which overrides the weak implementation in acpi/acpi.c. The call in arch/x86/mpspec.c can be ignored, since GENERATE_MP_TABLE isn't selected. So this change will result in the LAPIC address in the MADT being changed from 0 to to LAPIC_DEFAULT_BASE. Since the documentation of the Quark SoC mentions that it has a LAPIC on its one x86 core, this should work. TEST=None Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2f163bd608f0548abb0e8de90843d2a796b8ef6c Reviewed-on: https://review.coreboot.org/c/coreboot/+/58550 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
245 lines
6.3 KiB
Plaintext
245 lines
6.3 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0-only
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config SOC_INTEL_QUARK
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bool
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help
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Intel Quark support
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if SOC_INTEL_QUARK
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config CPU_SPECIFIC_OPTIONS
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def_bool y
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select ARCH_X86
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select NO_MMCONF_SUPPORT
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select REG_SCRIPT
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select PLATFORM_USES_FSP2_0
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select SOC_INTEL_COMMON
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select SOC_INTEL_COMMON_RESET
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select SOC_SETS_MSRS
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select SPI_FLASH
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select UART_OVERRIDE_REFCLK
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select UDELAY_TSC
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select TSC_MONOTONIC_TIMER
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select UNCOMPRESSED_RAMSTAGE
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select USE_MARCH_586
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select NO_SMM
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#####
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# Debug serial output
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# The following options configure the debug serial port
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#####
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config ENABLE_BUILTIN_HSUART0
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bool "Enable built-in HSUART0"
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default n
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select NO_UART_ON_SUPERIO
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select DRIVERS_UART_8250MEM_32
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help
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The Quark SoC has two HSUART. Choose this option to configure the pads
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and enable HSUART0, which can be used for the debug console.
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config ENABLE_BUILTIN_HSUART1
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bool "Enable built-in HSUART1"
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default n
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depends on ! ENABLE_BUILTIN_HSUART0
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select NO_UART_ON_SUPERIO
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select DRIVERS_UART_8250MEM_32
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help
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The Quark SoC has two HSUART. Choose this option to configure the pads
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and enable HSUART1, which can be used for the debug console.
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config TTYS0_BASE
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hex "HSUART Base Address"
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default 0xA0019000
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depends on ENABLE_BUILTIN_HSUART0 || ENABLE_BUILTIN_HSUART1
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help
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Memory mapped MMIO of HSUART.
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config TTYS0_LCS
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int
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default 3
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depends on ENABLE_BUILTIN_HSUART0 || ENABLE_BUILTIN_HSUART1
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# Console: PCI UART bus 0 << 20, device 20 << 15, function x << 12
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# Valid bit, PCI UART in use: 1 << 31
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config UART_PCI_ADDR
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hex
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default 0x800a1000 if ENABLE_BUILTIN_HSUART0
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default 0x800a5000 if ENABLE_BUILTIN_HSUART1
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depends on ENABLE_BUILTIN_HSUART0 || ENABLE_BUILTIN_HSUART1
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#####
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# Debug support
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# The following options provide debug support for the Quark coreboot
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# code. The SD LED is used as a binary marker to determine if a
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# specific point in the execution flow has been reached.
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#####
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config ENABLE_DEBUG_LED
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bool
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default n
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help
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Enable the use of the SD LED for early debugging before serial output
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is available. Setting this LED indicates that control has reached the
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desired check point.
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config ENABLE_DEBUG_LED_ESRAM
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bool "SD LED indicates ESRAM initialized"
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default n
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select ENABLE_DEBUG_LED
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help
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Indicate that ESRAM has been successfully initialized. If the SD LED
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does not light then the ESRAM initialization needs to be debugged.
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config ENABLE_DEBUG_LED_BOOTBLOCK_ENTRY
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bool "SD LED indicates bootblock.c successfully entered"
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default n
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select ENABLE_DEBUG_LED
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help
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Indicate that bootblock_c_entry was entered. If the SD LED does not
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light then debug the code between ESRAM and bootblock_c_entry.
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config ENABLE_DEBUG_LED_SOC_EARLY_INIT_ENTRY
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bool "SD LED indicates bootblock_soc_early_init successfully entered"
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default n
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select ENABLE_DEBUG_LED
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help
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Indicate that bootblock_soc_early_init was entered. If the SD LED
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does not light then debug the code in bootblock_main_with_timestamp.
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config ENABLE_DEBUG_LED_SOC_EARLY_INIT_EXIT
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bool "SD LED indicates bootblock_soc_early_init successfully exited"
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default n
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select ENABLE_DEBUG_LED
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help
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Indicate that bootblock_soc_early_init exited. If the SD LED does not
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light then debug the scripts in bootblock_soc_early_init.
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config ENABLE_DEBUG_LED_SOC_INIT_ENTRY
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bool "SD LED indicates bootblock_soc_init successfully entered"
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default n
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select ENABLE_DEBUG_LED
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help
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Indicate that bootblock_soc_init was entered. If the SD LED does not
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light then debug the code in bootblock_mainboard_early_init and
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console_init. If the SD LED does light but there is no serial then
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debug the serial port configuration and initialization.
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#####
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# ESRAM layout
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# Specify the portion of the ESRAM for coreboot to use as its data area.
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#####
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config DCACHE_RAM_BASE
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hex
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default 0x80000000
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config DCACHE_RAM_SIZE
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hex
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default 0x40000
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config DISPLAY_ESRAM_LAYOUT
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bool "Display ESRAM layout"
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default n
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help
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Select this option to display coreboot's use of ESRAM.
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#####
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# Flash layout
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# Specify the size of the coreboot file system in the read-only
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# (recovery) portion of the flash part.
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#####
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config CBFS_SIZE
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default 0x200000
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help
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Specify the size of the coreboot file system in the read-only (recovery)
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portion of the flash part. On Quark systems the firmware image stores
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more than just coreboot, including:
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- The chipset microcode (RMU) binary file located at 0xFFF00000
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- Intel Trusted Execution Engine firmware
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#####
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# FSP binary
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# The following options control the FSP binary file placement in
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# the flash image and ESRAM. This file is required by the Quark
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# SoC code to boot coreboot and its payload.
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#####
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config FSP_ESRAM_LOC
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hex
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default 0x80040000
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help
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The location in ESRAM where a copy of the FSP binary is placed.
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config FSP_M_FILE
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string
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default "3rdparty/blobs/soc/intel/quark/\$(CONFIG_FSP_TYPE)/\$(CONFIG_FSP_BUILD_TYPE)/FSP_M.fd"
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config FSP_S_FILE
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string
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default "3rdparty/blobs/soc/intel/quark/\$(CONFIG_FSP_TYPE)/\$(CONFIG_FSP_BUILD_TYPE)/FSP_S.fd"
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#####
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# RMU binary
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# The following options control the Quark chipset microcode file
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# placement in the flash image. This file is required to bring
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# the Quark processor out of reset.
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#####
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config ADD_RMU_FILE
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bool "Should the RMU binary be added to the flash image?"
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default n
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help
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The RMU file is required to get the chip out of reset.
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config RMU_FILE
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string
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default "3rdparty/blobs/soc/intel/quark/rmu.bin"
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depends on ADD_RMU_FILE
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help
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The path and filename of the Intel Quark RMU binary.
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config RMU_LOC
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hex
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default 0xfff00000
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depends on ADD_RMU_FILE
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help
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The location in CBFS that the RMU is located. It must match the
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strap-determined base address.
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config DCACHE_BSP_STACK_SIZE
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hex
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default 0x4000
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#####
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# Test support
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#####
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config STORAGE_TEST
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bool "Test SD/MMC/eMMC card or device access"
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default n
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select COMMONLIB_STORAGE
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select SDHCI_CONTROLLER
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help
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Read block 0 from each partition of the storage device. User
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must also enable one or both of COMMONLIB_STORAGE_SD or
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COMMONLIB_STORAGE_MMC.
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config STORAGE_LOG
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bool "Log and display SD/MMC commands"
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default n
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depends on STORAGE_TEST
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#####
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# I2C debug support
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#####
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config I2C_DEBUG
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bool "Enable I2C debugging"
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default n
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help
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Display the I2C segments and controller errors
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endif # SOC_INTEL_QUARK
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