cf52f9761f
- Align register values. - Enable both EHCI and XHCI so the choice of port used can be made at runtime. When both are enabled in devicetree, XHCI currently gets disabled by the FSP chipset code. This can be overridden in mainboard code or by a Kconfig entry, but there's a question about whether or not that's desired. - Enable function 1c.0 so the rest of the functions will be seen, even though the function is not actually used. This is a short-term fix, as the correct solution is to determine whether or not any of the other functions are enabled, and not to hide function 0 if they are. I am working on that, but I want to get this in for now. Change-Id: I83ae12c2393024b82a55d0b3a5ffa8782e16107e Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7663 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
98 lines
4.7 KiB
Plaintext
98 lines
4.7 KiB
Plaintext
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
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## Copyright (C) 2014 Intel Corporation
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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chip soc/intel/fsp_baytrail
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#### ACPI Register Settings ####
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register "fadt_pm_profile" = "PM_UNSPECIFIED"
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register "fadt_boot_arch" = "ACPI_FADT_LEGACY_FREE"
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#### FSP register settings ####
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register "PcdSataMode" = "SATA_MODE_AHCI"
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register "PcdMrcInitSPDAddr1" = "SPD_ADDR_DEFAULT"
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register "PcdMrcInitSPDAddr2" = "SPD_ADDR_DEFAULT"
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register "PcdMrcInitMmioSize" = "MMIO_SIZE_DEFAULT"
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register "PcdeMMCBootMode" = "EMMC_FOLLOWS_DEVICETREE"
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register "PcdIgdDvmt50PreAlloc" = "IGD_MEMSIZE_DEFAULT"
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register "PcdApertureSize" = "APERTURE_SIZE_DEFAULT"
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register "PcdGttSize" = "GTT_SIZE_DEFAULT"
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register "PcdLpssSioEnablePciMode" = "LPSS_PCI_MODE_DEFAULT"
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register "AzaliaAutoEnable" = "AZALIA_FOLLOWS_DEVICETREE"
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register "LpeAcpiModeEnable" = "LPE_ACPI_MODE_DISABLED"
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register "IgdRenderStandby" = "IGD_RENDER_STANDBY_ENABLE"
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register "EnableMemoryDown" = "MEMORY_DOWN_ENABLE"
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register "DRAMSpeed" = "DRAM_SPEED_1066MHZ"
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register "DRAMType" = "DRAM_TYPE_DDR3L"
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register "DIMM0Enable" = "DIMM0_ENABLE"
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register "DIMM1Enable" = "DIMM1_DISABLE"
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register "DIMMDWidth" = "DIMM_DWIDTH_X16"
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register "DIMMDensity" = "DIMM_DENSITY_2G_BIT" # Setting for 1GB board - modified runtime for 2GB board in romstage.c to DIMM_DENSITY_4G_BIT
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register "DIMMBusWidth" = "DIMM_BUS_WIDTH_64BIT"
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register "DIMMSides" = "DIMM_SIDES_1RANK"
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register "DIMMtCL" = "11"
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register "DIMMtRPtRCD" = "11"
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register "DIMMtWR" = "12"
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register "DIMMtWTR" = "6"
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register "DIMMtRRD" = "6"
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register "DIMMtRTP" = "6"
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register "DIMMtFAW" = "20"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device domain 0 on
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device pci 00.0 on end # 8086 0F00 - SoC router -
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device pci 02.0 on end # 8086 0F31 - GFX micro HDMI
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device pci 03.0 off end # 8086 0F38 - MIPI -
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device pci 10.0 off end # 8086 0F14 - EMMC Port -
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device pci 11.0 off end # 8086 0F15 - SDIO Port -
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device pci 12.0 on end # 8086 0F16 - SD Port MicroSD on SD3
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device pci 13.0 on end # 8086 0F23 - SATA AHCI Onboard & HSEC
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device pci 14.0 on end # 8086 0F35 - USB XHCI - Onboard & HSEC - Enabling both EHCI and XHCI will default to EHCI if not changed at runtime
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device pci 15.0 on end # 8086 0F28 - LP Engine Audio LSEC
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device pci 17.0 off end # 8086 0F50 - MMC Port -
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device pci 18.0 on end # 8086 0F40 - SIO - DMA -
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device pci 18.1 off end # 8086 0F41 - I2C Port 1 (0) -
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device pci 18.2 on end # 8086 0F42 - I2C Port 2 (1) - (testpoints)
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device pci 18.3 off end # 8086 0F43 - I2C Port 3 (2) -
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device pci 18.4 off end # 8086 0F44 - I2C Port 4 (3) -
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device pci 18.5 off end # 8086 0F45 - I2C Port 5 (4) -
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device pci 18.6 on end # 8086 0F46 - I2C Port 6 (5) LSEC
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device pci 18.7 on end # 8086 0F47 - I2C Port 7 (6) HSEC
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device pci 1a.0 on end # 8086 0F18 - TXE -
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device pci 1b.0 off end # 8086 0F04 - HD Audio -
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device pci 1c.0 on end # 8086 0F48 - PCIe Port 1 (0) -
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device pci 1c.1 off end # 8086 0F4A - PCIe Port 2 (1) -
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device pci 1c.2 on end # 8086 0F4C - PCIe Port 3 (2) Onboard GBE
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device pci 1c.3 on end # 8086 0F4E - PCIe Port 4 (3) HSEC
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device pci 1d.0 on end # 8086 0F34 - USB EHCI - Enabling both EHCI and XHCI will default to EHCI if not changed at runtime
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device pci 1e.0 on end # 8086 0F06 - SIO - DMA -
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device pci 1e.1 on end # 8086 0F08 - PWM 1 LSEC
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device pci 1e.2 on end # 8086 0F09 - PWM 2 LSEC
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device pci 1e.3 on end # 8086 0F0A - HSUART 1 LSEC
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device pci 1e.4 on end # 8086 0F0C - HSUART 2 LSEC
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device pci 1e.5 on end # 8086 0F0E - SPI LSEC
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device pci 1f.0 on end # 8086 0F1C - LPC bridge No connector
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device pci 1f.3 on end # 8086 0F12 - SMBus 0 SPC
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end
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end
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