cff071ab0e
files for targets without failover: src/config/nofailovercalculation.lb (64 kB XIP) src/config/nofailovercalculation128.lb (128 kB XIP) Targets with other XIP sizes were ignored. This patch moves XIP size back into mainboard code. Benefits from this patch: - src/config/nofailovercalculation128.lb is no longer needed - Targets with XIP sizes besides 64k and 128k benefit from refactoring - Conceptually, this makes the include files pure calculation files without settings. Abuild tested. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4348 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
176 lines
4.1 KiB
Plaintext
176 lines
4.1 KiB
Plaintext
##
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## Only use the option table in a normal image
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##
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default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
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## XIP_ROM_SIZE must be a power of 2.
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default XIP_ROM_SIZE = 128 * 1024
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include /config/nofailovercalculation.lb
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##
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## Set all of the defaults for an x86 architecture
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##
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arch i386 end
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##
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## Build the objects we have code for in this directory.
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##
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driver mainboard.o
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if HAVE_MP_TABLE object mptable.o end
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if HAVE_PIRQ_TABLE object irq_tables.o end
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object reset.o
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##
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## Romcc output
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##
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makerule ./failover.E
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depends "$(MAINBOARD)/failover.c ../romcc"
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action "../romcc -fno-simplify-phi -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
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end
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makerule ./failover.inc
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depends "$(MAINBOARD)/failover.c ../romcc"
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action "../romcc -fno-simplify-phi -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
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end
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makerule ./auto.E
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depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
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action "../romcc -fno-simplify-phi -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
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end
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makerule ./auto.inc
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depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
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action "../romcc -fno-simplify-phi -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
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end
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##
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## Build our 16 bit and 32 bit coreboot entry code
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##
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mainboardinit cpu/x86/16bit/entry16.inc
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mainboardinit cpu/x86/32bit/entry32.inc
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ldscript /cpu/x86/16bit/entry16.lds
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ldscript /cpu/x86/32bit/entry32.lds
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##
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## Build our reset vector (This is where coreboot is entered)
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##
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if USE_FALLBACK_IMAGE
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mainboardinit cpu/x86/16bit/reset16.inc
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ldscript /cpu/x86/16bit/reset16.lds
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else
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mainboardinit cpu/x86/32bit/reset32.inc
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ldscript /cpu/x86/32bit/reset32.lds
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end
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### Should this be in the northbridge code?
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mainboardinit arch/i386/lib/cpu_reset.inc
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##
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## Include an id string (For safe flashing)
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##
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mainboardinit arch/i386/lib/id.inc
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ldscript /arch/i386/lib/id.lds
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###
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### This is the early phase of coreboot startup
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### Things are delicate and we test to see if we should
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### failover to another image.
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###
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if USE_FALLBACK_IMAGE
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ldscript /arch/i386/lib/failover.lds
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mainboardinit ./failover.inc
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end
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###
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### O.k. We aren't just an intermediary anymore!
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###
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##
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## Setup RAM
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##
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mainboardinit cpu/x86/fpu/enable_fpu.inc
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mainboardinit cpu/x86/mmx/enable_mmx.inc
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mainboardinit cpu/x86/sse/enable_sse.inc
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mainboardinit ./auto.inc
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mainboardinit cpu/x86/sse/disable_sse.inc
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mainboardinit cpu/x86/mmx/disable_mmx.inc
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##
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## Include the secondary Configuration files
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##
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dir /pc80
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config chip.h
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chip northbridge/intel/e7520 # mch
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device pci_domain 0 on
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chip southbridge/intel/i82801er # i82801er
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# USB ports
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device pci 1d.0 on end
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device pci 1d.1 on end
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device pci 1d.2 on end
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device pci 1d.3 on end
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device pci 1d.7 on end
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# -> Bridge
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device pci 1e.0 on end
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# -> ISA
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device pci 1f.0 on
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chip superio/nsc/pc8374
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device pnp 2e.0 off end
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device pnp 2e.1 off end
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device pnp 2e.2 off end
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device pnp 2e.3 on
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.4 off end
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device pnp 2e.5 off end
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device pnp 2e.6 off end
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device pnp 2e.7 off end
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device pnp 2e.8 off end
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end
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end
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# -> IDE
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device pci 1f.1 on end
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# -> SATA
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device pci 1f.2 on end
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device pci 1f.3 on end
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register "pirq_a_d" = "0x8a07030b"
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register "pirq_e_h" = "0x85808080"
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end
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device pci 00.0 on end
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device pci 00.1 on end
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device pci 01.0 on end
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device pci 02.0 on
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chip southbridge/intel/pxhd # pxhd1
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# Bus bridges and ioapics usually bus 1
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device pci 0.0 on
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# On board gig e1000
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chip drivers/generic/generic
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device pci 03.0 on end
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device pci 03.1 on end
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end
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end
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device pci 0.1 on end
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device pci 0.2 on end
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device pci 0.3 on end
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end
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end
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device pci 04.0 on end
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device pci 06.0 on end
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end
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device apic_cluster 0 on
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chip cpu/intel/socket_mPGA604 # cpu 0
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device apic 0 on end
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end
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chip cpu/intel/socket_mPGA604 # cpu 1
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device apic 6 on end
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end
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end
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register "intrline" = "0x00070100"
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end
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