cff479e930
This change adds a driver pcie_gpp.c which provides device_operations for external and internal PCIe GPP bridges. These device operations include standard PCI bridge operations as well as operations for generating ACPI node for the device and returning appropriate ACPI name for it. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I9f8809c2735bdc09435deda91a570c89e71e8062 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43312 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
146 lines
3.4 KiB
C
146 lines
3.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <drivers/i2c/designware/dw_i2c.h>
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#include <soc/acpi.h>
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#include <soc/cpu.h>
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#include <soc/data_fabric.h>
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#include <soc/iomap.h>
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#include <soc/pci_devs.h>
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#include <soc/southbridge.h>
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#include "chip.h"
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#include <fsp/api.h>
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/* Supplied by i2c.c */
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extern struct device_operations picasso_i2c_mmio_ops;
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/* Supplied by uart.c */
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extern struct device_operations picasso_uart_mmio_ops;
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struct device_operations cpu_bus_ops = {
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.read_resources = noop_read_resources,
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.set_resources = noop_set_resources,
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.init = mp_cpu_bus_init,
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.acpi_fill_ssdt = generate_cpu_entries,
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};
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const char *soc_acpi_name(const struct device *dev)
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{
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if (dev->path.type == DEVICE_PATH_DOMAIN)
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return "PCI0";
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if (dev->path.type == DEVICE_PATH_USB) {
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switch (dev->path.usb.port_type) {
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case 0:
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/* Root Hub */
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return "RHUB";
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case 3:
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/* USB3 ports */
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switch (dev->path.usb.port_id) {
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case 0: return "SS01";
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case 1: return "SS02";
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case 2: return "SS03";
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}
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break;
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}
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return NULL;
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}
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if (dev->path.type != DEVICE_PATH_PCI)
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return NULL;
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if (dev->bus->dev->path.type == DEVICE_PATH_DOMAIN) {
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switch (dev->path.pci.devfn) {
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case GNB_DEVFN:
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return "GNB";
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case IOMMU_DEVFN:
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return "IOMM";
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case LPC_DEVFN:
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return "LPCB";
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case SMBUS_DEVFN:
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return "SBUS";
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default:
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printk(BIOS_WARNING, "Unknown root PCI device: dev: %d, fn: %d\n",
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PCI_SLOT(dev->path.pci.devfn), PCI_FUNC(dev->path.pci.devfn));
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return NULL;
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}
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}
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if (dev->bus->dev->path.type == DEVICE_PATH_PCI
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&& dev->bus->dev->path.pci.devfn == PCIE_GPP_A_DEVFN) {
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switch (dev->path.pci.devfn) {
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case XHCI0_DEVFN:
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return "XHC0";
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case XHCI1_DEVFN:
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return "XHC1";
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default:
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printk(BIOS_WARNING, "Unknown Bus A PCI device: dev: %d, fn: %d\n",
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PCI_SLOT(dev->path.pci.devfn), PCI_FUNC(dev->path.pci.devfn));
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return NULL;
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}
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}
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printk(BIOS_WARNING, "Unknown PCI device: dev: %d, fn: %d\n",
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PCI_SLOT(dev->path.pci.devfn), PCI_FUNC(dev->path.pci.devfn));
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return NULL;
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};
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struct device_operations pci_domain_ops = {
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.read_resources = pci_domain_read_resources,
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.set_resources = pci_domain_set_resources,
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.scan_bus = pci_domain_scan_bus,
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.acpi_name = soc_acpi_name,
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};
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static void set_mmio_dev_ops(struct device *dev)
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{
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switch (dev->path.mmio.addr) {
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case APU_I2C2_BASE:
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case APU_I2C3_BASE:
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case APU_I2C4_BASE:
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dev->ops = &picasso_i2c_mmio_ops;
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break;
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case APU_UART0_BASE:
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case APU_UART1_BASE:
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case APU_UART2_BASE:
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case APU_UART3_BASE:
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dev->ops = &picasso_uart_mmio_ops;
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break;
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}
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}
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static void enable_dev(struct device *dev)
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{
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/* Set the operations if it is a special bus type */
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if (dev->path.type == DEVICE_PATH_DOMAIN) {
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dev->ops = &pci_domain_ops;
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} else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
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dev->ops = &cpu_bus_ops;
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} else if (dev->path.type == DEVICE_PATH_MMIO) {
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set_mmio_dev_ops(dev);
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}
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}
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static void soc_init(void *chip_info)
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{
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default_dev_ops_root.write_acpi_tables = agesa_write_acpi_tables;
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fsp_silicon_init(acpi_is_wakeup_s3());
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data_fabric_set_mmio_np();
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southbridge_init(chip_info);
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}
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static void soc_final(void *chip_info)
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{
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southbridge_final(chip_info);
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}
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struct chip_operations soc_amd_picasso_ops = {
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CHIP_NAME("AMD Picasso SOC")
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.enable_dev = enable_dev,
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.init = soc_init,
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.final = soc_final
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};
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