d023909b01
This fixes a hard to debug hang that could occur in any stage, but in the end it follows simple rules and is easy to fix. In long mode the 32bit displacement addressing used on 'mov' and 'lea' instructions is sign-extended. Those instructions can be found using readelf on the stage and searching for relocation type R_X86_64_32S. The sign extension is no issue when either running in protected mode or the code module and thus the address is below 2GiB. If the address is greater than 2GiB, as usually the case for code in TSEG, the higher address bits [64:32] are all set to 1 and the effective address is pointing to memory not paged. Accessing this memory will cause a page fault, which isn't handled either. To prevent such problems - disable R_AMD64_32S relocations in rmodtool - add comment explaining why it's not allowed - use the pseudo op movabs, which doesn't use 32bit displacement addressing - Print a useful error message if such a reloc is present in the code Fixes a crash in TSEG and when in long mode seen on Intel Sandybridge. Change-Id: Ia5f5a9cde7c325f67b12e3a8e9a76283cc3870a3 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55448 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
184 lines
3.4 KiB
ArmAsm
184 lines
3.4 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/cr.h>
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#include <cpu/x86/cache.h>
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.section ".module_parameters", "aw", @progbits
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/* stack_top indicates the stack to pull MTRR information from. */
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.global post_car_stack_top
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post_car_stack_top:
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.long 0
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.long 0
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#if defined(__x86_64__)
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.code64
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.macro pop_eax_edx
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pop %rax
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mov %rax, %rdx
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shr $32, %rdx
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.endm
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.macro pop_ebx_esi
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pop %rbx
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mov %rbx, %rsi
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shr $32, %rsi
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.endm
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#else
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.code32
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.macro pop_eax_edx
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pop %eax
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pop %edx
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.endm
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.macro pop_ebx_esi
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pop %ebx
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pop %esi
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.endm
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#endif
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.text
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.global _start
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_start:
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/* Assume stack alignment doesn't matter here as chipset_teardown_car
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is expected to be implemented in assembly. */
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/* Migrate GDT to this text segment */
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#if defined(__x86_64__)
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call gdt_init64
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#else
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call gdt_init
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#endif
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#ifdef __x86_64__
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mov %rdi, %rax
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movabs %rax, _cbmem_top_ptr
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#else
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/* The return argument is at 0(%esp), the calling argument at 4(%esp) */
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movl 4(%esp), %eax
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movl %eax, _cbmem_top_ptr
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#endif
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/* Make sure _cbmem_top_ptr hits dram before invd */
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movl $1, %eax
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cpuid
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btl $CPUID_FEATURE_CLFLUSH_BIT, %edx
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jnc skip_clflush
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#ifdef __x86_64__
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movabs _cbmem_top_ptr, %rax
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clflush (%rax)
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#else
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clflush _cbmem_top_ptr
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#endif
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skip_clflush:
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/* chipset_teardown_car() is expected to disable cache-as-ram. */
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call chipset_teardown_car
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/* Enable caching if not already enabled. */
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#ifdef __x86_64__
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mov %cr0, %rax
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and $(~(CR0_CD | CR0_NW)), %eax
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mov %rax, %cr0
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/* Ensure cache is clean. */
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invd
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/* Set up new stack. */
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movabs post_car_stack_top, %rax
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mov %rax, %rsp
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#else
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mov %cr0, %eax
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and $(~(CR0_CD | CR0_NW)), %eax
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mov %eax, %cr0
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/* Ensure cache is clean. */
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invd
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/* Set up new stack. */
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mov post_car_stack_top, %esp
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#endif
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/*
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* Honor variable MTRR information pushed on the stack with the
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* following layout:
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*
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* Offset: Value
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* ...
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* 0x14: MTRR mask 0 63:32
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* 0x10: MTRR mask 0 31:0
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* 0x0c: MTRR base 0 63:32
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* 0x08: MTRR base 0 31:0
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* 0x04: Number of variable MTRRs to set
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* 0x00: Number of variable MTRRs to clear
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*/
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#if CONFIG(SOC_SETS_MSRS)
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mov %esp, %ebp
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/* Need to align stack to 16 bytes at the call instruction. Therefore
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account for the 1 push. */
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andl $0xfffffff0, %esp
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#if defined(__x86_64__)
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mov %rbp, %rdi
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#else
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sub $12, %esp
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push %ebp
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#endif
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call soc_set_mtrrs
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/* Ignore fixing up %esp since we're setting it a new value. */
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/* eax: new top_of_stack with setup_stack_and_mtrrs data removed */
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movl %eax, %esp
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/* Align stack to 16 bytes at call instruction. */
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andl $0xfffffff0, %esp
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call soc_enable_mtrrs
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#else /* CONFIG_SOC_SETS_MSRS */
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/* Clear variable MTRRs. */
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pop_ebx_esi /* ebx: Number to clear, esi: Number to set */
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test %ebx, %ebx
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jz 2f
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xor %eax, %eax
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xor %edx, %edx
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mov $(MTRR_PHYS_BASE(0)), %ecx
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1:
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wrmsr
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inc %ecx
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wrmsr
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inc %ecx
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dec %ebx
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jnz 1b
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2:
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/* Set Variable MTRRs based on stack contents. */
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test %esi, %esi
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jz 2f
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mov $(MTRR_PHYS_BASE(0)), %ecx
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1:
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/* Write MTRR base. */
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pop_eax_edx
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wrmsr
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inc %ecx
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/* Write MTRR mask. */
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pop_eax_edx
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wrmsr
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inc %ecx
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dec %esi
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jnz 1b
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2:
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/* Enable MTRR. */
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mov $(MTRR_DEF_TYPE_MSR), %ecx
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rdmsr
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/* Make default type uncacheable. */
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and $(~(MTRR_DEF_TYPE_MASK)), %eax
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or $(MTRR_DEF_TYPE_EN), %eax
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wrmsr
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#endif /* CONFIG_SOC_SETS_MSRS */
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/* Align stack to 16 bytes at call instruction. */
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andl $0xfffffff0, %esp
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/* Call into main for postcar. */
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call main
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/* Should never return. */
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1:
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jmp 1b
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