d08be7eecd
Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4803 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
141 lines
3.8 KiB
Plaintext
141 lines
3.8 KiB
Plaintext
## CONFIG_XIP_ROM_SIZE must be a power of 2.
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default CONFIG_XIP_ROM_SIZE = 64 * 1024
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include /config/nofailovercalculation.lb
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##
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## Set all of the defaults for an x86 architecture
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##
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arch i386 end
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##
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## Build the objects we have code for in this directory.
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##
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driver mainboard.o
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if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
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#object reset.o
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##
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## Romcc output
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##
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makerule ./failover.E
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depends "$(CONFIG_MAINBOARD)/failover.c ../romcc"
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action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
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end
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makerule ./failover.inc
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depends "$(CONFIG_MAINBOARD)/failover.c ../romcc"
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action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
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end
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makerule ./auto.E
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depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
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action "../romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
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end
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makerule ./auto.inc
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depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
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action "../romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
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end
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##
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## Build our 16 bit and 32 bit coreboot entry code
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##
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mainboardinit cpu/x86/16bit/entry16.inc
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mainboardinit cpu/x86/32bit/entry32.inc
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ldscript /cpu/x86/16bit/entry16.lds
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ldscript /cpu/x86/32bit/entry32.lds
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##
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## Build our reset vector (This is where coreboot is entered)
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##
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if CONFIG_USE_FALLBACK_IMAGE
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mainboardinit cpu/x86/16bit/reset16.inc
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ldscript /cpu/x86/16bit/reset16.lds
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else
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mainboardinit cpu/x86/32bit/reset32.inc
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ldscript /cpu/x86/32bit/reset32.lds
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end
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### Should this be in the northbridge code?
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mainboardinit arch/i386/lib/cpu_reset.inc
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##
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## Include an id string (For safe flashing)
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##
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mainboardinit arch/i386/lib/id.inc
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ldscript /arch/i386/lib/id.lds
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###
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### This is the early phase of coreboot startup
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### Things are delicate and we test to see if we should
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### failover to another image.
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###
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if CONFIG_USE_FALLBACK_IMAGE
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ldscript /arch/i386/lib/failover.lds
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mainboardinit ./failover.inc
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end
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###
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### O.k. We aren't just an intermediary anymore!
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###
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##
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## Setup RAM
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##
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mainboardinit cpu/x86/fpu_enable.inc
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mainboardinit ./auto.inc
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##
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## Include the secondary Configuration files
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##
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dir /pc80
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config chip.h
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chip northbridge/amd/gx2
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register "irqmap" = "0xaa5b"
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register "setupflash" = "0"
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device apic_cluster 0 on
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chip cpu/amd/model_gx2
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device apic 0 on end
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end
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end
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device pci_domain 0 on
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device pci 1.0 on end
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device pci 1.1 on end
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chip southbridge/amd/cs5536
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# 0x51400025 (IRQ Mapper LPC Mask)= 0x00001002
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# IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK
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# 0x5140004E (LPC Serial IRQ Control) = 0xEFFD0080.
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# Frame Pulse Width = 4clocks
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# IRQ Data Frames = 17Frames
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# SIRQ Mode = continous , It would be better if the EC could operate in
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# Active(Quiet) mode. Save power....
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# SIRQ Enable = Enabled
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# Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK
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#register "lpc_irq" = "0x00001002"
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#register "lpc_serirq_enable" = "0xEFFD0080"
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#register "enable_gpio0_inta" = "1"
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#register "enable_ide_nand_flash" = "1"
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#register "enable_uarta" = "1"
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#register "enable_USBP4_host" = "1"
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#register "audio_irq" = "5"
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#register "usbf4_irq" = "10"
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#register "usbf5_irq" = "10"
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#register "usbf6_irq" = "0"
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#register "usbf7_irq" = "0"
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device pci d.0 on end # Realtek 8139 LAN
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device pci f.0 on end # ISA Bridge
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device pci f.2 on end # IDE Controller
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device pci f.3 on end # Audio
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device pci f.4 on end # OHCI
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device pci f.5 on end # EHCI
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register "unwanted_vpci[0]" = "0x80007E00" # USB/UDC
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register "unwanted_vpci[1]" = "0x80007F00" # USB/OTG
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register "unwanted_vpci[2]" = "0" # End of list has a zero
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end
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end
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end
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