d0b5164cd0
BUG=b:184162768 TEST=none Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id03454ed2be242bce9497560c089f75046ed7e32 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52197 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
33 lines
894 B
C
33 lines
894 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef CEZANNE_CHIP_H
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#define CEZANNE_CHIP_H
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#include <amdblocks/chip.h>
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#include <soc/i2c.h>
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#include <drivers/i2c/designware/dw_i2c.h>
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#include <types.h>
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struct soc_amd_cezanne_config {
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struct soc_amd_common_config common_config;
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u8 i2c_scl_reset;
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struct dw_i2c_bus_config i2c[I2C_CTRLR_COUNT];
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/* Enable S0iX support */
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bool s0ix_enable;
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enum {
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DOWNCORE_AUTO = 0,
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DOWNCORE_1 = 1, /* Run with 1 physical core */
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DOWNCORE_2 = 3, /* Run with 2 physical cores */
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DOWNCORE_3 = 4, /* Run with 3 physical cores */
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DOWNCORE_4 = 6, /* Run with 4 physical cores */
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DOWNCORE_5 = 8, /* Run with 5 physical cores */
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DOWNCORE_6 = 9, /* Run with 6 physical cores */
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DOWNCORE_7 = 10, /* Run with 7 physical cores */
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} downcore_mode;
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bool disable_smt; /* disable second thread on all physical cores */
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};
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#endif /* CEZANNE_CHIP_H */
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