This patch add support for PTL platform to the `spd_tools`. This would be useful to create dynamic SPD for fatcat variants. BUG=b:347669091 TEST=Able to generate SPD for LP5 DRAM part. Change-Id: I55c3f49439fb1ad961c6866f03594431e54279b9 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83822 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com>
9 lines
126 B
Plaintext
9 lines
126 B
Plaintext
# Generated by:
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# util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5
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PTL,set-0
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MTL,set-0
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ADL,set-0
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PHX,set-1
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MDN,set-1
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