Jordan Crouse fa36f5048f coreboot-v2: Disable second serial port on Norwich ...

There isn't really any good reason to have the second serial port
enabled on Norwich, and this makes the X DDC code stop working.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3294 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

2008-05-09 15:32:46 +00:00

..

arch

Don't check exclusive IRQ fieldin the PIR table.

2008-04-07 17:49:57 +00:00

boot

rename linuxbios_* files, too.

2008-01-18 16:16:45 +00:00

config

Now coreboot performs IRQ routing for some boards.

2008-03-29 16:59:27 +00:00

console

Rename almost all occurences of LinuxBIOS to coreboot.

2008-01-18 15:08:58 +00:00

cpu

Remove inline from FAM10 CPU initialization functions.

2008-04-25 21:34:25 +00:00

devices

Fix so pci device memory allocation does not use memory base address at 0xfec00000, this is reserved for APIC.

2008-04-25 02:02:33 +00:00

drivers

Rename almost all occurences of LinuxBIOS to coreboot.

2008-01-18 15:08:58 +00:00

include

Following patch adds K8M890 support. It initializes the AGP and graphics UMA.

2008-03-20 21:19:50 +00:00

lib

Clarify LZMA code license.

2008-03-17 01:37:27 +00:00

mainboard

coreboot-v2: Disable second serial port on Norwich

2008-05-09 15:32:46 +00:00

northbridge

Remove inline from FAM10 CPU initialization functions.

2008-04-25 21:34:25 +00:00

pc80

rename linuxbios_* files, too.

2008-01-18 16:16:45 +00:00

pmc/altimus/mpc7410

Please bear with me - another rename checkin. This qualifies as trivial, no

2008-01-18 10:35:56 +00:00

ram

Trivial: remove unused variable.

2007-10-22 17:04:39 +00:00

sdram

1201_ht_bus0_dev0_fidvid_core.diff

2005-12-02 21:52:30 +00:00

southbridge

Implement GPIO configuration routines for the Intel 3100 southbridge,

2008-05-07 21:57:12 +00:00

stream

Rename almost all occurences of LinuxBIOS to coreboot.

2008-01-18 15:08:58 +00:00

superio

This trivial patch adds the SMSC SCH3112 Super I/O chip ID to the

2008-04-19 13:32:19 +00:00