d149bfa17f
This change updates bootblock_pch_early_init() to perform P2SB configuration before any other PCH controllers are initialized. This is done because the other controllers might perform PCR settings which requires the PCR base address to be configured. As the PCR base address configuration happens during P2SB initialization, this change moves the p2sb init calls before any other PCH controller initialization. BUG=b:171534504 Change-Id: I485556be003ff5338b4e2046768fe4f6d8a619a3 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47885 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
157 lines
3.9 KiB
C
157 lines
3.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <console/console.h>
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#include <console/post_codes.h>
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#include <device/mmio.h>
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#include <device/device.h>
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#include <device/pci_ops.h>
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#include <intelblocks/fast_spi.h>
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#include <intelblocks/gspi.h>
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#include <intelblocks/lpc_lib.h>
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#include <intelblocks/p2sb.h>
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#include <intelblocks/pcr.h>
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#include <intelblocks/pmclib.h>
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#include <intelblocks/rtc.h>
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#include <soc/bootblock.h>
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#include <soc/espi.h>
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#include <soc/iomap.h>
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#include <soc/p2sb.h>
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#include <soc/pch.h>
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#include <soc/pci_devs.h>
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#include <soc/pcr_ids.h>
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#include <soc/pm.h>
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#define PCR_PSF3_TO_SHDW_PMC_REG_BASE 0xA00
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#define PCR_PSFX_TO_SHDW_BAR0 0
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#define PCR_PSFX_TO_SHDW_BAR1 0x4
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#define PCR_PSFX_TO_SHDW_BAR2 0x8
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#define PCR_PSFX_TO_SHDW_BAR3 0xC
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#define PCR_PSFX_TO_SHDW_BAR4 0x10
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#define PCR_PSFX_TO_SHDW_PCIEN_IOEN 0x01
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#define PCR_PSFX_T0_SHDW_PCIEN 0x1C
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#define PCR_DMI_DMICTL 0x2234
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#define PCR_DMI_DMICTL_SRLOCK (1 << 31)
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#define PCR_DMI_ACPIBA 0x27B4
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#define PCR_DMI_ACPIBDID 0x27B8
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#define PCR_DMI_PMBASEA 0x27AC
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#define PCR_DMI_PMBASEC 0x27B0
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#define PCR_DMI_LPCIOD 0x2770
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#define PCR_DMI_LPCIOE 0x2774
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static void soc_config_pwrmbase(void)
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{
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/*
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* Assign Resources to PWRMBASE
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* Clear BIT 1-2 Command Register
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*/
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pci_and_config16(PCH_DEV_PMC, PCI_COMMAND, ~(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
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/* Program PWRM Base */
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pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS);
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/* Enable Bus Master and MMIO Space */
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pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
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/* Enable PWRM in PMC */
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setbits32((void *) PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN);
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}
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void bootblock_pch_early_init(void)
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{
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/*
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* Perform P2SB configuration before any another controller initialization as the
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* controller might want to perform PCR settings.
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*/
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p2sb_enable_bar();
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p2sb_configure_hpet();
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fast_spi_early_init(SPI_BASE_ADDRESS);
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gspi_early_bar_init();
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/*
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* Enabling PWRM Base for accessing
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* Global Reset Cause Register.
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*/
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soc_config_pwrmbase();
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}
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static void soc_config_acpibase(void)
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{
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uint32_t pmc_reg_value;
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uint32_t pmc_base_reg = PCR_PSF3_TO_SHDW_PMC_REG_BASE;
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pmc_reg_value = pcr_read32(PID_PSF3, pmc_base_reg + PCR_PSFX_TO_SHDW_BAR4);
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if (pmc_reg_value != 0xffffffff) {
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/* Disable Io Space before changing the address */
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pcr_rmw32(PID_PSF3, pmc_base_reg + PCR_PSFX_T0_SHDW_PCIEN,
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~PCR_PSFX_TO_SHDW_PCIEN_IOEN, 0);
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/* Program ABASE in PSF3 PMC space BAR4*/
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pcr_write32(PID_PSF3, pmc_base_reg + PCR_PSFX_TO_SHDW_BAR4,
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ACPI_BASE_ADDRESS);
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/* Enable IO Space */
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pcr_rmw32(PID_PSF3, pmc_base_reg + PCR_PSFX_T0_SHDW_PCIEN,
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~0, PCR_PSFX_TO_SHDW_PCIEN_IOEN);
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}
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}
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static int pch_check_decode_enable(void)
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{
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uint32_t dmi_control;
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/*
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* This cycle decoding is only allowed to set when
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* DMICTL.SRLOCK is 0.
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*/
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dmi_control = pcr_read32(PID_DMI, PCR_DMI_DMICTL);
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if (dmi_control & PCR_DMI_DMICTL_SRLOCK)
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return -1;
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return 0;
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}
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void pch_early_iorange_init(void)
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{
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uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 |
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LPC_IOE_EC_62_66 | LPC_IOE_LGE_200;
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/* IO Decode Range */
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if (CONFIG(DRIVERS_UART_8250IO))
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lpc_io_setup_comm_a_b();
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/* IO Decode Enable */
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if (pch_check_decode_enable() == 0) {
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io_enables = lpc_enable_fixed_io_ranges(io_enables);
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/*
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* Set ESPI IO Enables PCR[DMI] + 2774h [15:0] to the same
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* value programmed in ESPI PCI offset 82h.
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*/
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pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables);
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/*
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* Set LPC IO Decode Ranges PCR[DMI] + 2770h [15:0] to the same
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* value programmed in LPC PCI offset 80h.
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*/
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pcr_write16(PID_DMI, PCR_DMI_LPCIOD, lpc_get_fixed_io_decode());
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}
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/* Program generic IO Decode Range */
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pch_enable_lpc();
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}
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void bootblock_pch_init(void)
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{
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/*
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* Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT,
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* GPE0_STS, GPE0_EN registers.
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*/
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soc_config_acpibase();
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/* Set up GPE configuration */
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pmc_gpe_init();
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enable_rtc_upper_bank();
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}
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