d21a329866
This patch is a raw application of the following spatch to the
directories src/arch/arm(64)?, src/mainboard/<arm(64)-board>,
src/soc/<arm(64)-soc> and src/drivers/gic:
@@
expression A, V;
@@
- write32(V, A)
+ writel(V, A)
@@
expression A, V;
@@
- write16(V, A)
+ writew(V, A)
@@
expression A, V;
@@
- write8(V, A)
+ writeb(V, A)
This replaces all uses of write{32,16,8}() with write{l,w,b}()
which is currently equivalent and much more common. This is a
preparatory step that will allow us to easier flip them all at once to
the new write32(a,v) model.
BRANCH=none
BUG=chromium:451388
TEST=Compiled Cosmos, Daisy, Blaze, Pit, Ryu, Storm and Pinky.
Change-Id: I16016cd77780e7cadbabe7d8aa7ab465b95b8f09
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 93f0ada19b429b4e30d67335b4e61d0f43597b24
Original-Change-Id: I1ac01c67efef4656607663253ed298ff4d0ef89d
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/254862
Reviewed-on: http://review.coreboot.org/9834
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
89 lines
2.5 KiB
C
89 lines
2.5 KiB
C
/*
|
|
* This file is part of the coreboot project.
|
|
*
|
|
* Copyright 2014 Google Inc.
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License as published by
|
|
* the Free Software Foundation; version 2 of the License.
|
|
*
|
|
* This program is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*
|
|
* You should have received a copy of the GNU General Public License
|
|
* along with this program; if not, write to the Free Software
|
|
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
|
*/
|
|
|
|
#include <arch/io.h>
|
|
#include <console/console.h>
|
|
#include <soc/addressmap.h>
|
|
#include <soc/clk_rst.h>
|
|
#include <soc/cpu.h>
|
|
#include <soc/pmc.h>
|
|
|
|
#define EVP_CPU_RESET_VECTOR (void *)(uintptr_t)(TEGRA_EVP_BASE + 0x100)
|
|
#define PMC_REGS (void *)(uintptr_t)(TEGRA_PMC_BASE)
|
|
|
|
static void enable_core_clocks(int cpu)
|
|
{
|
|
const uint32_t cpu0_clocks = CRC_RST_CPUG_CLR_CPU0 |
|
|
CRC_RST_CPUG_CLR_DBG0 |
|
|
CRC_RST_CPUG_CLR_CORE0 |
|
|
CRC_RST_CPUG_CLR_CX0;
|
|
const uint32_t cpu1_clocks = CRC_RST_CPUG_CLR_CPU1 |
|
|
CRC_RST_CPUG_CLR_DBG1 |
|
|
CRC_RST_CPUG_CLR_CORE1 |
|
|
CRC_RST_CPUG_CLR_CX1;
|
|
|
|
/* Clear reset of CPU components. */
|
|
if (cpu == 0)
|
|
writel(cpu0_clocks, CLK_RST_REG(rst_cpug_cmplx_clr));
|
|
else
|
|
writel(cpu1_clocks, CLK_RST_REG(rst_cpug_cmplx_clr));
|
|
}
|
|
|
|
static void set_armv8_32bit_reset_vector(uintptr_t entry)
|
|
{
|
|
void * const evp_cpu_reset_vector = EVP_CPU_RESET_VECTOR;
|
|
writel(entry, evp_cpu_reset_vector);
|
|
}
|
|
|
|
static void set_armv8_64bit_reset_vector(uintptr_t entry)
|
|
{
|
|
struct tegra_pmc_regs * const pmc = PMC_REGS;
|
|
|
|
/* Currently assume 32-bit addresses only. */
|
|
writel(entry, &pmc->secure_scratch34);
|
|
writel(0, &pmc->secure_scratch35);
|
|
}
|
|
|
|
void cpu_prepare_startup(void *entry_64)
|
|
{
|
|
/* Warm reset vector is pulled from the PMC scratch registers. */
|
|
set_armv8_64bit_reset_vector((uintptr_t)entry_64);
|
|
|
|
/*
|
|
* The Denver cores start in 32-bit mode. Therefore a trampoline
|
|
* is needed to get into 64-bit mode. Point the cold reset vector
|
|
* to the traompoline location.
|
|
*/
|
|
set_armv8_32bit_reset_vector((uintptr_t)reset_entry_32bit);
|
|
}
|
|
|
|
void start_cpu_silent(int cpu, void *entry_64)
|
|
{
|
|
cpu_prepare_startup(entry_64);
|
|
enable_core_clocks(cpu);
|
|
}
|
|
|
|
void start_cpu(int cpu, void *entry_64)
|
|
{
|
|
printk(BIOS_DEBUG, "Starting CPU%d @ %p trampolining to %p.\n",
|
|
cpu, reset_entry_32bit, entry_64);
|
|
|
|
start_cpu_silent(cpu, entry_64);
|
|
}
|