d21a329866
This patch is a raw application of the following spatch to the
directories src/arch/arm(64)?, src/mainboard/<arm(64)-board>,
src/soc/<arm(64)-soc> and src/drivers/gic:
@@
expression A, V;
@@
- write32(V, A)
+ writel(V, A)
@@
expression A, V;
@@
- write16(V, A)
+ writew(V, A)
@@
expression A, V;
@@
- write8(V, A)
+ writeb(V, A)
This replaces all uses of write{32,16,8}() with write{l,w,b}()
which is currently equivalent and much more common. This is a
preparatory step that will allow us to easier flip them all at once to
the new write32(a,v) model.
BRANCH=none
BUG=chromium:451388
TEST=Compiled Cosmos, Daisy, Blaze, Pit, Ryu, Storm and Pinky.
Change-Id: I16016cd77780e7cadbabe7d8aa7ab465b95b8f09
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 93f0ada19b429b4e30d67335b4e61d0f43597b24
Original-Change-Id: I1ac01c67efef4656607663253ed298ff4d0ef89d
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/254862
Reviewed-on: http://review.coreboot.org/9834
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
97 lines
2.9 KiB
C
97 lines
2.9 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <arch/io.h>
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#include <soc/addressmap.h>
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#include <soc/flow_ctrl.h>
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#define FLOW_CTRL_HALT_CPU0_EVENTS 0x0
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#define FLOW_CTRL_WAITEVENT (2 << 29)
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#define FLOW_CTRL_WAIT_FOR_INTERRUPT (4 << 29)
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#define FLOW_CTRL_HALT_LIC_IRQ (1 << 11)
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#define FLOW_CTRL_HALT_LIC_FIQ (1 << 10)
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#define FLOW_CTRL_CPU0_CSR 0x8
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#define FLOW_CTRL_CSR_INTR_FLAG (1 << 15)
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#define FLOW_CTRL_CSR_EVENT_FLAG (1 << 14)
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#define FLOW_CTRL_CSR_WFI_CPU0 (1 << 8)
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#define FLOW_CTRL_CSR_WFI_BITMAP (0xF << 8)
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#define FLOW_CTRL_CSR_WFE_BITMAP (0xF << 4)
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#define FLOW_CTRL_CSR_ENABLE (1 << 0)
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#define FLOW_CTRL_HALT_CPU1_EVENTS 0x14
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#define FLOW_CTRL_CPU1_CSR 0x18
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#define HALT_REG_CORE0 (\
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FLOW_CTRL_WAIT_FOR_INTERRUPT | \
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FLOW_CTRL_HALT_LIC_IRQ | \
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FLOW_CTRL_HALT_LIC_FIQ)
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#define HALT_REG_CORE1 FLOW_CTRL_WAITEVENT
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static void *tegra_flowctrl_base = (void*)TEGRA_FLOW_BASE;
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static const uint8_t flowctrl_offset_halt_cpu[] = {
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FLOW_CTRL_HALT_CPU0_EVENTS,
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FLOW_CTRL_HALT_CPU1_EVENTS
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};
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static const uint8_t flowctrl_offset_cpu_csr[] = {
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FLOW_CTRL_CPU0_CSR,
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FLOW_CTRL_CPU1_CSR
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};
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static uint32_t flowctrl_read_cpu_csr(int cpu)
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{
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return read32(tegra_flowctrl_base + flowctrl_offset_cpu_csr[cpu]);
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}
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static void flowctrl_write_cpu_csr(int cpu, uint32_t val)
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{
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writel(val, tegra_flowctrl_base + flowctrl_offset_cpu_csr[cpu]);
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val = readl(tegra_flowctrl_base + flowctrl_offset_cpu_csr[cpu]);
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}
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void flowctrl_write_cpu_halt(int cpu, uint32_t val)
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{
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writel(val, tegra_flowctrl_base + flowctrl_offset_halt_cpu[cpu]);
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val = readl(tegra_flowctrl_base + flowctrl_offset_halt_cpu[cpu]);
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}
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static void flowctrl_prepare_cpu_off(int cpu)
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{
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uint32_t reg;
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reg = flowctrl_read_cpu_csr(cpu);
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reg &= ~FLOW_CTRL_CSR_WFE_BITMAP; /* clear wfe bitmap */
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reg &= ~FLOW_CTRL_CSR_WFI_BITMAP; /* clear wfi bitmap */
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reg |= FLOW_CTRL_CSR_INTR_FLAG; /* clear intr flag */
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reg |= FLOW_CTRL_CSR_EVENT_FLAG; /* clear event flag */
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reg |= FLOW_CTRL_CSR_WFI_CPU0 << cpu; /* power gating on wfi */
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reg |= FLOW_CTRL_CSR_ENABLE; /* enable power gating */
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flowctrl_write_cpu_csr(cpu, reg);
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}
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void flowctrl_cpu_off(int cpu)
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{
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uint32_t reg;
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reg = cpu ? HALT_REG_CORE1 : HALT_REG_CORE0;
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flowctrl_prepare_cpu_off(cpu);
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flowctrl_write_cpu_halt(cpu, reg);
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}
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