d2ca5be61a
Alder Lake N SOC has eMMC device. Add ACPI ASL methods for it. Change-Id: I53f04e81584493049d37b46e078d394d3c8a2f09 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61127 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
48 lines
893 B
Plaintext
48 lines
893 B
Plaintext
/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <intelblocks/itss.h>
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#include <intelblocks/pcr.h>
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#include <soc/itss.h>
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#include <soc/pcr_ids.h>
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/* PCR access */
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#include <soc/intel/common/acpi/pcr.asl>
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/* PCH clock */
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#include "camera_clock_ctl.asl"
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/* GPIO controller */
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#include "gpio.asl"
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/* ESPI 0:1f.0 */
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#include <soc/intel/common/block/acpi/acpi/lpc.asl>
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/* PCH HDA */
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#include "pch_hda.asl"
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/* PCIE Ports */
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#include "pcie.asl"
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/* Serial IO */
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#include "serialio.asl"
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/* eMMC */
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#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N)
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#include "scs.asl"
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#endif
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/* SMBus 0:1f.4 */
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#include <soc/intel/common/block/acpi/acpi/smbus.asl>
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/* ISH 0:12.0 */
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#include <soc/intel/common/block/acpi/acpi/ish.asl>
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/* USB XHCI 0:14.0 */
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#include "xhci.asl"
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/* PCI _OSC */
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#include <soc/intel/common/acpi/pci_osc.asl>
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/* GbE 0:1f.6 */
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#include <soc/intel/common/block/acpi/acpi/pch_glan.asl>
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