bbf013c38f
CBFS could start from below 4MB, and should be cacheable for the purpose of early microcode update and CBFS search for romstage file. Change-Id: Ia2a1c6e5fdcc3201fafc8cf5c841cebbbf0b30c9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4626 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com>
123 lines
3.4 KiB
C
123 lines
3.4 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <stdint.h>
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#include <arch/cpu.h>
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#include <cpu/x86/cache.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/mtrr.h>
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#include <arch/io.h>
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#include <cpu/intel/microcode/microcode.c>
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#include "model_206ax.h"
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#if CONFIG_SOUTHBRIDGE_INTEL_BD82X6X || CONFIG_SOUTHBRIDGE_INTEL_C216
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/* Needed for RCBA access to set Soft Reset Data register */
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#include <southbridge/intel/bd82x6x/pch.h>
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#else
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#error "CPU must be paired with Intel BD82X6X or C216 southbridge"
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#endif
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static void set_var_mtrr(
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unsigned reg, unsigned base, unsigned size, unsigned type)
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{
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/* Bit Bit 32-35 of MTRRphysMask should be set to 1 */
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/* FIXME: It only support 4G less range */
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msr_t basem, maskm;
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basem.lo = base | type;
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basem.hi = 0;
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wrmsr(MTRRphysBase_MSR(reg), basem);
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maskm.lo = ~(size - 1) | MTRRphysMaskValid;
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maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1;
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wrmsr(MTRRphysMask_MSR(reg), maskm);
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}
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static void enable_rom_caching(void)
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{
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msr_t msr;
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disable_cache();
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set_var_mtrr(1, CACHE_ROM_BASE, CACHE_ROM_SIZE, MTRR_TYPE_WRPROT);
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enable_cache();
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/* Enable Variable MTRRs */
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msr.hi = 0x00000000;
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msr.lo = 0x00000800;
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wrmsr(MTRRdefType_MSR, msr);
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}
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static void set_flex_ratio_to_tdp_nominal(void)
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{
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msr_t flex_ratio, msr;
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u32 soft_reset;
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u8 nominal_ratio;
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/* Minimum CPU revision for configurable TDP support */
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if (cpuid_eax(1) < IVB_CONFIG_TDP_MIN_CPUID)
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return;
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/* Check for Flex Ratio support */
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flex_ratio = rdmsr(MSR_FLEX_RATIO);
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if (!(flex_ratio.lo & FLEX_RATIO_EN))
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return;
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/* Check for >0 configurable TDPs */
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msr = rdmsr(MSR_PLATFORM_INFO);
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if (((msr.hi >> 1) & 3) == 0)
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return;
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/* Use nominal TDP ratio for flex ratio */
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msr = rdmsr(MSR_CONFIG_TDP_NOMINAL);
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nominal_ratio = msr.lo & 0xff;
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/* See if flex ratio is already set to nominal TDP ratio */
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if (((flex_ratio.lo >> 8) & 0xff) == nominal_ratio)
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return;
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/* Set flex ratio to nominal TDP ratio */
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flex_ratio.lo &= ~0xff00;
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flex_ratio.lo |= nominal_ratio << 8;
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flex_ratio.lo |= FLEX_RATIO_LOCK;
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wrmsr(MSR_FLEX_RATIO, flex_ratio);
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/* Set flex ratio in soft reset data register bits 11:6.
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* RCBA region is enabled in southbridge bootblock */
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soft_reset = RCBA32(SOFT_RESET_DATA);
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soft_reset &= ~(0x3f << 6);
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soft_reset |= (nominal_ratio & 0x3f) << 6;
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RCBA32(SOFT_RESET_DATA) = soft_reset;
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/* Set soft reset control to use register value */
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RCBA32_OR(SOFT_RESET_CTRL, 1);
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/* Issue warm reset, will be "CPU only" due to soft reset data */
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outb(0x0, 0xcf9);
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outb(0x6, 0xcf9);
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asm("hlt");
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}
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static void bootblock_cpu_init(void)
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{
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/* Set flex ratio and reset if needed */
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set_flex_ratio_to_tdp_nominal();
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enable_rom_caching();
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intel_update_microcode_from_cbfs();
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}
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