d351925446
All K8/Fam10h boards use CAR, so move the "select CACHE_AS_RAM" into the socket directories, and remove it from the individual boards. Do the same for Intel CPUs/sockets where all boards use CAR. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6151 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
83 lines
1.3 KiB
Plaintext
83 lines
1.3 KiB
Plaintext
if BOARD_AMD_PISTACHIO
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select ARCH_X86
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select CPU_AMD_SOCKET_AM2
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select DIMM_DDR2
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select NORTHBRIDGE_AMD_AMDK8
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select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
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select SOUTHBRIDGE_AMD_RS690
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select SOUTHBRIDGE_AMD_SB600
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select BOARD_HAS_FADT
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select HAVE_BUS_CONFIG
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select HAVE_OPTION_TABLE
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select HAVE_PIRQ_TABLE
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select HAVE_MP_TABLE
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select HAVE_HARD_RESET
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select SB_HT_CHAIN_UNITID_OFFSET_ONLY
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select WAIT_BEFORE_CPUS_INIT
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select HAVE_ACPI_TABLES
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select BOARD_ROMSIZE_KB_1024
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select RAMINIT_SYSINFO
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select QRANK_DIMM_SUPPORT
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select SET_FIDVID
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config MAINBOARD_DIR
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string
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default amd/pistachio
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config DCACHE_RAM_BASE
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hex
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default 0xc8000
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config DCACHE_RAM_SIZE
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hex
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default 0x08000
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config DCACHE_RAM_GLOBAL_VAR_SIZE
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hex
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default 0x01000
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config APIC_ID_OFFSET
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hex
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default 0x0
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config MAINBOARD_PART_NUMBER
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string
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default "Pistachio"
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config MAX_CPUS
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int
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default 2
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config MAX_PHYSICAL_CPUS
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int
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default 1
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config SB_HT_CHAIN_ON_BUS0
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int
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default 1
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config HT_CHAIN_END_UNITID_BASE
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hex
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default 0x1
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config HT_CHAIN_UNITID_BASE
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hex
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default 0x0
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config IRQ_SLOT_COUNT
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int
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default 11
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config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
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hex
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default 0x1022
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config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
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hex
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default 0x3050
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endif # BOARD_AMD_PISTACHIO
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