d37aeb1bcb
The clock driver supports configuring the general purpose PLLs, configuring the root clock generator (RCG), enable clock branch, enable gdsc and also the block resets. The common clock driver exposes PLL configuration functions and also different Agera PLL enable functions for the CPU PLLs. While at it, the common driver also supports reset of subsystems like AOP and SHRM. SC7180 clock driver is also refactored to use the common clock driver APIs. BUG=b:182963902 TEST=Validated on qualcomm sc7180 and sc7280 development board. Change-Id: I03d1b4a2fb90303c7259ec08f312d78b4e33ec39 Signed-off-by: Taniya Das <tdas@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
140 lines
4.8 KiB
Makefile
140 lines
4.8 KiB
Makefile
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ifeq ($(CONFIG_SOC_QUALCOMM_SC7180),y)
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decompressor-y += decompressor.c
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decompressor-y += mmu.c
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decompressor-y += ../common/timer.c
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all-y += ../common/timer.c
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all-y += spi.c
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all-y += ../common/gpio.c
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all-y += qupv3_i2c.c
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all-y += qupv3_spi.c
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all-y += clock.c
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all-$(CONFIG_SC7180_QSPI) += qspi.c
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all-y += ../common/clock.c
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all-y += qcom_qup_se.c
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all-y += qupv3_config.c
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################################################################################
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bootblock-y += bootblock.c
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bootblock-y += mmu.c
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bootblock-$(CONFIG_DRIVERS_UART) += ../common/uart_bitbang.c
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################################################################################
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verstage-$(CONFIG_DRIVERS_UART) += qupv3_uart.c
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################################################################################
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romstage-y += cbmem.c
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romstage-y += watchdog.c
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romstage-y += ../common/qclib.c
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romstage-y += ../common/mmu.c
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romstage-y += mmu.c
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romstage-y += usb.c
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romstage-y += carve_out.c
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romstage-$(CONFIG_DRIVERS_UART) += qupv3_uart.c
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################################################################################
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ramstage-y += soc.c
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ramstage-y += carve_out.c
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ramstage-y += aop_load_reset.c
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ramstage-y += usb.c
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ramstage-$(CONFIG_DRIVERS_UART) += qupv3_uart.c
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ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += display/dsi_phy_pll.c
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ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += display/dsi_phy.c
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ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += display/dsi.c
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ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += display/mdss.c
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################################################################################
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CPPFLAGS_common += -Isrc/soc/qualcomm/sc7180/include
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CPPFLAGS_common += -Isrc/soc/qualcomm/common/include
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BL31_MAKEARGS += PLAT=sc7180
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SC7180_BLOB := $(top)/3rdparty/qc_blobs/sc7180
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ifeq ($(CONFIG_QC_SDI_ENABLE),y)
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BL31_MAKEARGS += QTI_SDI_BUILD=1
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BL31_MAKEARGS += QTISECLIB_PATH=$(SC7180_BLOB)/qtiseclib/libqtisec_dbg.a
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else
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BL31_MAKEARGS += QTISECLIB_PATH=$(SC7180_BLOB)/qtiseclib/libqtisec.a
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endif # CONFIG_QC_SDI_ENABLE
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################################################################################
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ifeq ($(CONFIG_QC_SDI_ENABLE),y)
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QCSDI_FILE := $(SC7180_BLOB)/boot/QcSdi.elf
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QCSDI_CBFS := $(CONFIG_CBFS_PREFIX)/qcsdi
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$(QCSDI_CBFS)-file := $(QCSDI_FILE)
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$(QCSDI_CBFS)-type := stage
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$(QCSDI_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
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cbfs-files-y += $(QCSDI_CBFS)
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endif
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################################################################################
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QCLIB_FILE := $(SC7180_BLOB)/boot/QcLib.elf
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QCLIB_CBFS := $(CONFIG_CBFS_PREFIX)/qclib
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$(QCLIB_CBFS)-file := $(QCLIB_FILE)
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$(QCLIB_CBFS)-type := stage
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$(QCLIB_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG)
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cbfs-files-y += $(QCLIB_CBFS)
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################################################################################
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PMIC_FILE := $(SC7180_BLOB)/boot/Pmic.bin
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PMIC_CBFS := $(CONFIG_CBFS_PREFIX)/pmiccfg
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$(PMIC_CBFS)-file := $(PMIC_FILE)
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$(PMIC_CBFS)-type := raw
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$(PMIC_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
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cbfs-files-y += $(PMIC_CBFS)
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################################################################################
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DCB_FILE := $(SC7180_BLOB)/boot/dcb.bin
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DCB_CBFS := $(CONFIG_CBFS_PREFIX)/dcb
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$(DCB_CBFS)-file := $(DCB_FILE)
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$(DCB_CBFS)-type := raw
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$(DCB_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
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cbfs-files-y += $(DCB_CBFS)
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################################################################################
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AOP_FILE := $(SC7180_BLOB)/aop/aop.mbn
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AOP_CBFS := $(CONFIG_CBFS_PREFIX)/aop
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$(AOP_CBFS)-file := $(AOP_FILE)
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$(AOP_CBFS)-type := payload
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$(AOP_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
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cbfs-files-y += $(AOP_CBFS)
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################################################################################
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UART_FW_FILE := $(SC7180_BLOB)/qup_fw/uart_fw.bin
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UART_FW_CBFS := $(CONFIG_CBFS_PREFIX)/uart_fw
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$(UART_FW_CBFS)-file := $(UART_FW_FILE)
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$(UART_FW_CBFS)-type := raw
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$(UART_FW_CBFS)-compression := none
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cbfs-files-y += $(UART_FW_CBFS)
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################################################################################
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SPI_FW_FILE := $(SC7180_BLOB)/qup_fw/spi_fw.bin
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SPI_FW_CBFS := $(CONFIG_CBFS_PREFIX)/spi_fw
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$(SPI_FW_CBFS)-file := $(SPI_FW_FILE)
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$(SPI_FW_CBFS)-type := raw
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$(SPI_FW_CBFS)-compression := none
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cbfs-files-y += $(SPI_FW_CBFS)
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################################################################################
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I2C_FW_FILE := $(SC7180_BLOB)/qup_fw/i2c_fw.bin
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I2C_FW_CBFS := $(CONFIG_CBFS_PREFIX)/i2c_fw
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$(I2C_FW_CBFS)-file := $(I2C_FW_FILE)
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$(I2C_FW_CBFS)-type := raw
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$(I2C_FW_CBFS)-compression := none
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cbfs-files-y += $(I2C_FW_CBFS)
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################################################################################
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QC_SEC_FILE := $(SC7180_BLOB)/qc_sec/qc_sec.mbn
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$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.elf
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@util/qualcomm/createxbl.py --mbn_version 6 -f $(objcbfs)/bootblock.raw.elf \
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-x $(QC_SEC_FILE) -o $(objcbfs)/merged_bb_qcsec.mbn \
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-a 64 -d 64 -c 64
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@printf "\nqgpt.py 4K sector size\n"
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@util/qualcomm/qgpt.py $(objcbfs)/merged_bb_qcsec.mbn \
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$(objcbfs)/bootblock.bin
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endif
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