d44221f9c8
Its spreading copies got out of sync. And as it is not a standard header but used in commonlib code, it belongs into commonlib. While we are at it, always include it via GCC's `-include` switch. Some Windows and BSD quirk handling went into the util copies. We always guard from redefinitions now to prevent further issues. Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
111 lines
2.6 KiB
C
111 lines
2.6 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2011 Allwinner Technology Co., Ltd.
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* Tom Cubie <tangliang@allwinnertech.com>
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* Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License or (at your option)
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* any later version
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Definitions for timer control on Allwinner CPUs
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*/
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#ifndef CPU_ALLWINNER_A10_TIMER_H
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#define CPU_ALLWINNER_A10_TIMER_H
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#include "memmap.h"
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#include <types.h>
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/* TMRx_CTRL values */
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#define TIMER_CTRL_MODE_SINGLE (1 << 7)
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#define TIMER_CTRL_PRESC_MASK (0x7 << 4)
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#define TIMER_CTRL_PRESC_DIV_EXP(ep) ((ep << 4) & TIMER_CTRL_PRESC_MASK)
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#define TIMER_CTRL_CLK_SRC_MASK (0x3 << 2)
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#define TIMER_CTRL_CLK_SRC_LOSC (0x0 << 2)
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#define TIMER_CTRL_CLK_SRC_OSC24M (0x1 << 2)
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#define TIMER_CTRL_CLK_SRC_PLL6 (0x2 << 2)
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#define TIMER_CTRL_RELOAD (1 << 1)
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#define TIMER_CTRL_TMR_EN (1 << 0)
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/* Chip revision definitions (found in CPU_CFG register) */
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#define A1X_CHIP_REV_A 0x0
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#define A1X_CHIP_REV_C1 0x1
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#define A1X_CHIP_REV_C2 0x2
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#define A1X_CHIP_REV_B 0x3
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/* General purpose timer */
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struct a1x_timer {
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u32 ctrl;
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u32 interval;
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u32 val;
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u8 res[4];
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} __packed;
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/* Audio video sync*/
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struct a1x_avs {
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u32 ctrl; /* 0x80 */
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u32 cnt0; /* 0x84 */
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u32 cnt1; /* 0x88 */
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u32 div; /* 0x8c */
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} __packed;
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/* Watchdog */
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struct a1x_wdog {
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u32 ctrl; /* 0x90 */
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u32 mode; /* 0x94 */
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} __packed;
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/* 64 bit counter */
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struct a1x_64cnt {
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u32 ctrl; /* 0xa0 */
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u32 lo; /* 0xa4 */
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u32 hi; /* 0xa8 */
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} __packed;
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/* Rtc */
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struct a1x_rtc {
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u32 ctrl; /* 0x100 */
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u32 yymmdd; /* 0x104 */
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u32 hhmmss; /* 0x108 */
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} __packed;
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/* Alarm */
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struct a1x_alarm {
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u32 ddhhmmss; /* 0x10c */
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u32 hhmmss; /* 0x110 */
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u32 en; /* 0x114 */
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u32 irq_en; /* 0x118 */
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u32 irq_sta; /* 0x11c */
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} __packed;
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struct a1x_timer_module {
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u32 irq_en; /* 0x00 */
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u32 irq_sta; /* 0x04 */
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u8 res1[8];
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struct a1x_timer timer[6]; /* We have 6 timers */
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u8 res2[16];
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struct a1x_avs avs;
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struct a1x_wdog wdog;
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u8 res3[8];
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struct a1x_64cnt cnt64;
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u8 res4[0x58];
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struct a1x_rtc rtc;
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struct a1x_alarm alarm;
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u32 gp_data[4];
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u8 res5[8];
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u32 cpu_cfg;
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} __packed;
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u8 a1x_get_cpu_chip_revision(void);
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#endif /* CPU_ALLWINNER_A10_TIMER_H */
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