d48d5a626b
Instantiate the touchpad using the drivers/i2c/generic device driver to generate the ACPI object in the SSDT. There is not currently a separate wake pin for this device, this will be added in EVT hardware. This was tested on the reef board by ensuring that the touchpad device continues to work in the OS. Also remove the LPC TPM from the DSDT as it is not present. Change-Id: I3151a28f628e66f63033398d6fab9fd8f5dfc37b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15481 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
94 lines
3.2 KiB
Plaintext
94 lines
3.2 KiB
Plaintext
chip soc/intel/apollolake
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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register "pcie_rp4_clkreq_pin" = "0" # wifi/bt
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# TODO(furquan): Remove this once global reset issue is fixed in later
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# steppings.
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# Integrated Sensor Hub
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register "integrated_sensor_hub_enable" = "1"
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# EMMC TX DATA Delay 1#
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# 0x0C[14:8] stands for 12*125 = 1500 pSec delay for HS400
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# 0x11[6:0] stands for 17*125 = 2125 pSec delay for SDR104/HS200
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register "emmc_tx_data_cntl1" = "0x0C11" # HS400 required
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# EMMC TX DATA Delay 2#
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# 0x00[30:24] stands for 0*125 = no delay for SDR50
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# 0x2B[22:16] stands for 43*125 = 5375 pSec delay for DDR50
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# 0x29[14:8] stands for 41*125 = 5125 pSec delay for SDR25/HS50
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# 0x29[6:0] stands for 41*125 = 5125 pSec delay for SDR12
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register "emmc_tx_data_cntl2" = "0x002B2929"
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# EMMC RX CMD/DATA Delay 1#
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# 0x00[30:24] stands for 0*125 = no delay for SDR50
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# 0x12[22:16] stands for 18*125 = 2250 pSec delay for DDR50
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# 0x57[14:8] stands for 87*125 = 10875 pSec delay for SDR25/HS50
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# 0x3B[6:0] stands for 59*125= 7375 pSec delay for SDR12
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register "emmc_rx_cmd_data_cntl1" = "0x0012573B"
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# EMMC RX CMD/DATA Delay 2#
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# 0x01[17:16] stands for Rx Clock before Output Buffer
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# 0x00[14:8] stands for 0 delay for Auto Tuning Mode
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# 0x1C[6:0] stands for 28*125 = 3500 pSec delay for HS200
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register "emmc_rx_cmd_data_cntl2" = "0x1001C"
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device domain 0 on
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device pci 00.0 on end # - Host Bridge
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device pci 00.1 on end # - DPTF
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device pci 00.2 on end # - NPK
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device pci 02.0 on end # - Gen
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device pci 03.0 on end # - Iunit
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device pci 0d.0 on end # - P2SB
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device pci 0d.1 on end # - PMC
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device pci 0d.2 on end # - SPI
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device pci 0d.3 on end # - Shared SRAM
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device pci 0e.0 on end # - Audio
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device pci 11.0 on end # - ISH
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device pci 12.0 off end # - SATA
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device pci 13.0 off end # - Root Port 2 - PCIe-A 0
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device pci 13.1 off end # - Root Port 3 - PCIe-A 1
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device pci 13.2 off end # - Root Port 4 - PCIe-A 2
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device pci 13.3 off end # - Root Port 5 - PCIe-A 3
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device pci 14.0 on end # - Root Port 0 - PCIe-B 0 - Wifi
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device pci 14.1 off end # - Root Port 1 - PCIe-B 1
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device pci 15.0 on end # - XHCI
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device pci 15.1 off end # - XDCI
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device pci 16.0 on end # - I2C 0
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device pci 16.1 on end # - I2C 1
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device pci 16.2 on end # - I2C 2
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device pci 16.3 on end # - I2C 3
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device pci 17.0 on
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chip drivers/i2c/generic
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register "hid" = ""ELAN0000""
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register "desc" = ""ELAN Touchpad""
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register "irq" = "IRQ_EDGE_LOW(GPIO_18_IRQ)"
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device i2c 15 on end
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end
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end # - I2C 4
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device pci 17.1 on end # - I2C 5
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device pci 17.2 on end # - I2C 6
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device pci 17.3 on end # - I2C 7
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device pci 18.0 on end # - UART 0
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device pci 18.1 on end # - UART 1
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device pci 18.2 on end # - UART 2
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device pci 18.3 on end # - UART 3
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device pci 19.0 on end # - SPI 0
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device pci 19.1 on end # - SPI 1
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device pci 19.2 on end # - SPI 2
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device pci 1a.0 on end # - PWM
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device pci 1b.0 on end # - SDCARD
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device pci 1c.0 on end # - eMMC
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device pci 1e.0 off end # - SDIO
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device pci 1f.0 on # - LPC
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chip ec/google/chromeec
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device pnp 0c09.0 on end
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end
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end
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device pci 1f.1 on end # - SMBUS
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end
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end
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