a96d6a9dab
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@828 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
149 lines
2.9 KiB
C
149 lines
2.9 KiB
C
static void outb(unsigned char value, unsigned short port)
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{
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__builtin_outb(value, port);
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}
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static void outl(unsigned int value, unsigned short port)
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{
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__builtin_outl(value, port);
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}
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static unsigned char inb(unsigned short port)
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{
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return __builtin_inb(port);
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}
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static unsigned char inl(unsigned short port)
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{
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return __builtin_inl(port);
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}
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static unsigned int config_cmd(unsigned char bus, unsigned devfn, unsigned where)
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{
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return 0x80000000 | (bus << 16) | (devfn << 8) | (where & ~3);
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}
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static unsigned int pcibios_read_config_dword(
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unsigned char bus, unsigned devfn, unsigned where)
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{
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outl(config_cmd(bus, devfn, where), 0xCF8);
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return inl(0xCFC);
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}
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/* Base Address */
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#ifndef TTYS0_BASE
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#define TTYS0_BASE 0x3f8
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#endif
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#ifndef TTYS0_BAUD
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#define TTYS0_BAUD 115200
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#endif
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#if ((115200%TTYS0_BAUD) != 0)
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#error Bad ttys0 baud rate
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#endif
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#define TTYS0_DIV (115200/TTYS0_BAUD)
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/* Line Control Settings */
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#ifndef TTYS0_LCS
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/* Set 8bit, 1 stop bit, no parity */
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#define TTYS0_LCS 0x3
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#endif
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#define UART_LCS TTYS0_LCS
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/* Data */
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#define UART_RBR 0x00
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#define UART_TBR 0x00
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/* Control */
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#define UART_IER 0x01
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#define UART_IIR 0x02
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#define UART_FCR 0x02
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#define UART_LCR 0x03
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#define UART_MCR 0x04
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#define UART_DLL 0x00
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#define UART_DLM 0x01
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/* Status */
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#define UART_LSR 0x05
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#define UART_MSR 0x06
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#define UART_SCR 0x07
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int uart_can_tx_byte(void)
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{
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return inb(TTYS0_BASE + UART_LSR) & 0x20;
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}
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void uart_wait_to_tx_byte(void)
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{
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while(!uart_can_tx_byte())
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;
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}
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void uart_wait_until_sent(void)
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{
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while(!(inb(TTYS0_BASE + UART_LSR) & 0x40))
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;
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}
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void uart_tx_byte(unsigned char data)
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{
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uart_wait_to_tx_byte();
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outb(data, TTYS0_BASE + UART_TBR);
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/* Make certain the data clears the fifos */
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uart_wait_until_sent();
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}
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void uart_init(void)
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{
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/* disable interrupts */
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outb(0x0, TTYS0_BASE + UART_IER);
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/* enable fifo's */
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outb(0x01, TTYS0_BASE + UART_FCR);
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/* Set Baud Rate Divisor to 12 ==> 115200 Baud */
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outb(0x80 | UART_LCS, TTYS0_BASE + UART_LCR);
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outb(TTYS0_DIV & 0xFF, TTYS0_BASE + UART_DLL);
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outb((TTYS0_DIV >> 8) & 0xFF, TTYS0_BASE + UART_DLM);
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outb(UART_LCS, TTYS0_BASE + UART_LCR);
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}
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void __console_tx_char(unsigned char byte)
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{
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uart_tx_byte(byte);
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}
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void __console_tx_nibble(unsigned nibble)
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{
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unsigned char digit;
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digit = nibble + '0';
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if (digit > '9') {
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digit += 39;
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}
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__console_tx_char(digit);
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}
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void __console_tx_hex32(unsigned int value)
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{
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__console_tx_nibble((value >> 28) & 0x0f);
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__console_tx_nibble((value >> 24) & 0x0f);
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__console_tx_nibble((value >> 20) & 0x0f);
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__console_tx_nibble((value >> 16) & 0x0f);
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__console_tx_nibble((value >> 12) & 0x0f);
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__console_tx_nibble((value >> 8) & 0x0f);
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__console_tx_nibble((value >> 4) & 0x0f);
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__console_tx_nibble(value & 0x0f);
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}
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void print_debug_hex32(unsigned int value) { __console_tx_hex32(value); }
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void main(void)
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{
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unsigned long htic;
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htic = pcibios_read_config_dword(0, 0xc0, 0x6c);
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print_debug_hex32(htic);
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}
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