d5811378dc
Change-Id: I916f19e022633b316fbc0c6bf38bbd58228412be Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56218 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao Reviewed-by: Angel Pons <th3fanbus@gmail.com>
107 lines
3.4 KiB
C
107 lines
3.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <device/pci_ops.h>
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#include <acpi/acpi.h>
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#include <cpu/x86/smm.h>
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#include <southbridge/intel/lynxpoint/pch.h>
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#include "chip.h"
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void acpi_fill_fadt(acpi_fadt_t *fadt)
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{
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struct device *dev = pcidev_on_root(0x1f, 0);
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struct southbridge_intel_lynxpoint_config *cfg = dev->chip_info;
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u16 pmbase = get_pmbase();
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fadt->sci_int = 0x9;
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if (permanent_smi_handler()) {
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fadt->smi_cmd = APM_CNT;
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fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
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fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
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}
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fadt->pm1a_evt_blk = pmbase + PM1_STS;
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fadt->pm1a_cnt_blk = pmbase + PM1_CNT;
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fadt->pm2_cnt_blk = pmbase + PM2_CNT;
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fadt->pm_tmr_blk = pmbase + PM1_TMR;
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if (pch_is_lp())
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fadt->gpe0_blk = pmbase + LP_GPE0_STS_1;
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else
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fadt->gpe0_blk = pmbase + GPE0_STS;
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/*
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* Some of the lengths here are doubled. This is because they describe
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* blocks containing two registers, where the size of each register
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* is found by halving the block length. See Table 5-34 and section
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* 4.8.3 of the ACPI specification for details.
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*/
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fadt->pm1_evt_len = 2 * 2;
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fadt->pm1_cnt_len = 2;
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fadt->pm2_cnt_len = 1;
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fadt->pm_tmr_len = 4;
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if (pch_is_lp())
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fadt->gpe0_blk_len = 2 * 16;
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else
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fadt->gpe0_blk_len = 2 * 8;
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/* P_LVLx not used */
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fadt->p_lvl2_lat = 101;
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fadt->p_lvl3_lat = 1001;
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fadt->duty_offset = 0;
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fadt->duty_width = 0;
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fadt->day_alrm = 0xd;
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fadt->mon_alrm = 0x00;
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fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
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fadt->flags |= ACPI_FADT_WBINVD |
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ACPI_FADT_C1_SUPPORTED |
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ACPI_FADT_SLEEP_BUTTON |
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ACPI_FADT_SEALED_CASE |
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ACPI_FADT_S4_RTC_WAKE |
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ACPI_FADT_PLATFORM_CLOCK;
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if (cfg && cfg->docking_supported)
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fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED;
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fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
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fadt->x_pm1a_evt_blk.bit_width = 2 * 16;
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fadt->x_pm1a_evt_blk.bit_offset = 0;
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fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
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fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS;
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fadt->x_pm1a_evt_blk.addrh = 0x0;
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fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
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fadt->x_pm1a_cnt_blk.bit_width = 16;
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fadt->x_pm1a_cnt_blk.bit_offset = 0;
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fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
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fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT;
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fadt->x_pm1a_cnt_blk.addrh = 0x0;
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fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
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fadt->x_pm2_cnt_blk.bit_width = 8;
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fadt->x_pm2_cnt_blk.bit_offset = 0;
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fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
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fadt->x_pm2_cnt_blk.addrl = pmbase + PM2_CNT;
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fadt->x_pm2_cnt_blk.addrh = 0x0;
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fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO;
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fadt->x_pm_tmr_blk.bit_width = 32;
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fadt->x_pm_tmr_blk.bit_offset = 0;
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fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
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fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR;
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fadt->x_pm_tmr_blk.addrh = 0x0;
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/*
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* Windows 10 requires x_gpe0_blk to be set starting with FADT revision 5.
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* The bit_width field intentionally overflows here.
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* The OSPM can instead use the values in `fadt->gpe0_blk{,_len}`, which
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* seems to work fine on Linux 5.0 and Windows 10.
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*/
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fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;
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fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8;
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fadt->x_gpe0_blk.bit_offset = 0;
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fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
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fadt->x_gpe0_blk.addrl = fadt->gpe0_blk;
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fadt->x_gpe0_blk.addrh = 0x0;
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}
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