d6161d46ff
The PSP does the memory training and setting up of MSRs for TOP_MEM and TOM2. Set caching up for all the DRAM areas: Enable WB caching for 1MiB->TOP_MEM, 4GiB->TOM2. Enable WC caching fro 0->1MiB except 0xa0000->0xc0000. BUG=b:155426691 Change-Id: I83916a220ea4016d4438dd4fb5be82dec5506f80 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
107 lines
3.2 KiB
C
107 lines
3.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <stdint.h>
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#include <symbols.h>
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#include <bootblock_common.h>
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#include <console/console.h>
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#include <cpu/x86/cache.h>
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#include <cpu/x86/msr.h>
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#include <cpu/amd/msr.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/amd/mtrr.h>
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#include <soc/southbridge.h>
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#include <soc/i2c.h>
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#include <amdblocks/amd_pci_mmconf.h>
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/* PSP performs the memory training and setting up DRAM map prior to x86 cores
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being released. Honor TOP_MEM and set up caching from 0 til TOP_MEM. Likewise,
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route lower memory addresses covered by fixed MTRRs to DRAM except for
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0xa0000-0xc0000 . */
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static void set_caching(void)
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{
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msr_t top_mem;
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msr_t sys_cfg;
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msr_t mtrr_def_type;
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msr_t fixed_mtrr_ram;
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msr_t fixed_mtrr_mmio;
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struct var_mtrr_context mtrr_ctx;
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var_mtrr_context_init(&mtrr_ctx, NULL);
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top_mem = rdmsr(TOP_MEM);
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/* Enable RdDram and WrDram attributes in fixed MTRRs. */
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sys_cfg = rdmsr(SYSCFG_MSR);
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sys_cfg.lo |= SYSCFG_MSR_MtrrFixDramModEn;
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/* Fixed MTRR constants. */
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fixed_mtrr_ram.lo = fixed_mtrr_ram.hi =
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((MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM) << 0) |
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((MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM) << 8) |
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((MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM) << 16) |
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((MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM) << 24);
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fixed_mtrr_mmio.lo = fixed_mtrr_mmio.hi =
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((MTRR_TYPE_UNCACHEABLE) << 0) |
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((MTRR_TYPE_UNCACHEABLE) << 8) |
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((MTRR_TYPE_UNCACHEABLE) << 16) |
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((MTRR_TYPE_UNCACHEABLE) << 24);
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/* Prep default MTRR type. */
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mtrr_def_type = rdmsr(MTRR_DEF_TYPE_MSR);
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mtrr_def_type.lo &= ~MTRR_DEF_TYPE_MASK;
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mtrr_def_type.lo |= MTRR_TYPE_UNCACHEABLE;
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mtrr_def_type.lo |= MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN;
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disable_cache();
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wrmsr(SYSCFG_MSR, sys_cfg);
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clear_all_var_mtrr();
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var_mtrr_set(&mtrr_ctx, 0, ALIGN_DOWN(top_mem.lo, 8*MiB), MTRR_TYPE_WRBACK);
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var_mtrr_set(&mtrr_ctx, FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);
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/* Set up RAM caching for everything below 1MiB except for 0xa0000-0xc0000 . */
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wrmsr(MTRR_FIX_64K_00000, fixed_mtrr_ram);
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wrmsr(MTRR_FIX_16K_80000, fixed_mtrr_ram);
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wrmsr(MTRR_FIX_16K_A0000, fixed_mtrr_mmio);
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wrmsr(MTRR_FIX_4K_C0000, fixed_mtrr_ram);
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wrmsr(MTRR_FIX_4K_C8000, fixed_mtrr_ram);
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wrmsr(MTRR_FIX_4K_D0000, fixed_mtrr_ram);
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wrmsr(MTRR_FIX_4K_D8000, fixed_mtrr_ram);
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wrmsr(MTRR_FIX_4K_E0000, fixed_mtrr_ram);
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wrmsr(MTRR_FIX_4K_E8000, fixed_mtrr_ram);
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wrmsr(MTRR_FIX_4K_F0000, fixed_mtrr_ram);
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wrmsr(MTRR_FIX_4K_F8000, fixed_mtrr_ram);
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wrmsr(MTRR_DEF_TYPE_MSR, mtrr_def_type);
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/* Enable Fixed and Variable MTRRs. */
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sys_cfg.lo |= SYSCFG_MSR_MtrrFixDramEn | SYSCFG_MSR_MtrrVarDramEn;
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sys_cfg.lo |= SYSCFG_MSR_TOM2En | SYSCFG_MSR_TOM2WB;
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/* AGESA currently expects SYSCFG_MSR_MtrrFixDramModEn to be set. Once
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MP init happens in coreboot proper it can be knocked down. */
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wrmsr(SYSCFG_MSR, sys_cfg);
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enable_cache();
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}
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asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
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{
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set_caching();
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enable_pci_mmconf();
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bootblock_main_with_basetime(base_timestamp);
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}
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void bootblock_soc_early_init(void)
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{
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fch_pre_init();
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}
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void bootblock_soc_init(void)
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{
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u32 val = cpuid_eax(1);
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printk(BIOS_DEBUG, "Family_Model: %08x\n", val);
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fch_early_init();
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}
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