d67edcae6e
Initially, I wanted to move only the Kconfig DISPLAY_MTRRS into the "Debug" menu. It turned out, though, that the code looks rather generic. No need to hide it in soc/intel/. To not bloat src/Kconfig up any further, start a new `Kconfig.debug` hierarchy just for debug options. If somebody wants to review the code if it's 100% generic, we could even get rid of HAVE_DISPLAY_MTRRS. Change-Id: Ibd0a64121bd6e4ab5d7fd835f3ac25d3f5011f24 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/29684 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
118 lines
3.3 KiB
C
118 lines
3.3 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2015 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/early_variables.h>
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#include <console/console.h>
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#include <cpu/x86/mtrr.h>
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#include <fsp/car.h>
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#include <fsp/util.h>
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#include <program_loading.h>
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#include <timestamp.h>
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FSP_INFO_HEADER *fih_car CAR_GLOBAL;
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/* Save FSP_INFO_HEADER for TempRamExit() call in assembly. */
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static inline void set_fih_car(FSP_INFO_HEADER *fih)
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{
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/* This variable is written in the raw form because it's only
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* ever accessed in code that that has the cache-as-ram enabled. The
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* assembly routine which tears down cache-as-ram utilizes this
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* variable for determining where to find FSP. */
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fih_car = fih;
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}
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asmlinkage void *cache_as_ram_main(struct cache_as_ram_params *car_params)
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{
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/* Initialize timestamp book keeping only once. */
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timestamp_init(car_params->tsc);
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/* Call into pre-console init code then initialize console. */
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car_soc_pre_console_init();
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car_mainboard_pre_console_init();
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console_init();
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printk(BIOS_DEBUG, "FSP TempRamInit successful\n");
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printk(BIOS_SPEW, "bist: 0x%08x\n", car_params->bist);
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printk(BIOS_SPEW, "tsc: 0x%016llx\n", car_params->tsc);
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if (car_params->bootloader_car_start != CONFIG_DCACHE_RAM_BASE ||
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car_params->bootloader_car_end !=
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(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)) {
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printk(BIOS_INFO, "CAR mismatch: %08x--%08x vs %08lx--%08lx\n",
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CONFIG_DCACHE_RAM_BASE,
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CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE,
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(long)car_params->bootloader_car_start,
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(long)car_params->bootloader_car_end);
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}
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car_soc_post_console_init();
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car_mainboard_post_console_init();
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set_fih_car(car_params->fih);
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/* Return new stack value in RAM back to assembly stub. */
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return cache_as_ram_stage_main(car_params->fih);
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}
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/* Entry point taken when romstage is called after a separate verstage. */
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asmlinkage void *romstage_c_entry(void)
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{
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/* Need to locate the current FSP_INFO_HEADER. The cache-as-ram
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* is still enabled. We can directly access work buffer here. */
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FSP_INFO_HEADER *fih;
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struct prog fsp = PROG_INIT(PROG_REFCODE, "fsp.bin");
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console_init();
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if (prog_locate(&fsp)) {
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fih = NULL;
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printk(BIOS_ERR, "Unable to locate %s\n", prog_name(&fsp));
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} else
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/* This leaks a mapping which this code assumes is benign as
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* the flash is memory mapped CPU's address space. */
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fih = find_fsp((uintptr_t)rdev_mmap_full(prog_rdev(&fsp)));
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set_fih_car(fih);
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/* Return new stack value in RAM back to assembly stub. */
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return cache_as_ram_stage_main(fih);
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}
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asmlinkage void after_cache_as_ram(void *chipset_context)
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{
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timestamp_add_now(TS_FSP_TEMP_RAM_EXIT_END);
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printk(BIOS_DEBUG, "FspTempRamExit returned successfully\n");
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display_mtrrs();
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after_cache_as_ram_stage();
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}
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void __weak car_mainboard_pre_console_init(void)
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{
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}
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void __weak car_soc_pre_console_init(void)
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{
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}
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void __weak car_mainboard_post_console_init(void)
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{
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}
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void __weak car_soc_post_console_init(void)
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{
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}
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