d67edcae6e
Initially, I wanted to move only the Kconfig DISPLAY_MTRRS into the "Debug" menu. It turned out, though, that the code looks rather generic. No need to hide it in soc/intel/. To not bloat src/Kconfig up any further, start a new `Kconfig.debug` hierarchy just for debug options. If somebody wants to review the code if it's 100% generic, we could even get rid of HAVE_DISPLAY_MTRRS. Change-Id: Ibd0a64121bd6e4ab5d7fd835f3ac25d3f5011f24 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/29684 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
124 lines
3.5 KiB
C
124 lines
3.5 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google Inc.
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* Copyright (C) 2015-2017 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <bootblock_common.h>
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#include <console/console.h>
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#include <cpu/x86/mtrr.h>
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#include <device/pci_def.h>
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#include <program_loading.h>
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#include <soc/iomap.h>
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#include <soc/pci_devs.h>
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#include <soc/reg_access.h>
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extern void asmlinkage light_sd_led(void);
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static const struct reg_script legacy_gpio_init[] = {
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/* Temporarily enable the legacy GPIO controller */
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REG_PCI_WRITE32(R_QNC_LPC_GBA_BASE, IO_ADDRESS_VALID
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| LEGACY_GPIO_BASE_ADDRESS),
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/* Temporarily enable the GPE controller */
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REG_PCI_WRITE32(R_QNC_LPC_GPE0BLK, IO_ADDRESS_VALID
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| GPE0_BASE_ADDRESS),
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REG_PCI_OR8(PCI_COMMAND, PCI_COMMAND_IO),
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REG_SCRIPT_END
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};
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static const struct reg_script i2c_gpio_controller_init[] = {
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/* Temporarily enable the GPIO controller */
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REG_PCI_WRITE32(PCI_BASE_ADDRESS_0, I2C_BASE_ADDRESS),
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REG_PCI_WRITE32(PCI_BASE_ADDRESS_1, GPIO_BASE_ADDRESS),
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REG_PCI_OR8(PCI_COMMAND, PCI_COMMAND_MEMORY),
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REG_SCRIPT_END
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};
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static const struct reg_script hsuart_init[] = {
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/* Enable the HSUART */
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REG_PCI_WRITE32(PCI_BASE_ADDRESS_0, UART_BASE_ADDRESS),
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REG_PCI_OR8(PCI_COMMAND, PCI_COMMAND_MEMORY),
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REG_SCRIPT_END
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};
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static const struct reg_script mtrr_init[] = {
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/* Use write-through caching, for FSP 2.0 the cache will be invalidated
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* postchar (arch/x86/exit_car.S).
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*/
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/* Enable the cache */
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REG_CPU_CR_AND(0, ~(CR0_CD | CR0_NW)),
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/* Cache the SPI flash */
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REG_MSR_WRITE(MTRR_PHYS_BASE(0), (uint32_t)((-CONFIG_ROM_SIZE)
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| MTRR_TYPE_WRTHROUGH)),
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REG_MSR_WRITE(MTRR_PHYS_MASK(0), (uint32_t)((-CONFIG_ROM_SIZE)
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| MTRR_PHYS_MASK_VALID)),
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/* Cache ESRAM */
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REG_MSR_WRITE(MTRR_PHYS_BASE(1), (uint32_t)(0x80000000
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| MTRR_TYPE_WRTHROUGH)),
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REG_MSR_WRITE(MTRR_PHYS_MASK(1), (uint32_t)((~0x7ffff)
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| MTRR_PHYS_MASK_VALID)),
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/* Enable the variable MTRRs */
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REG_MSR_WRITE(MTRR_DEF_TYPE_MSR, MTRR_DEF_TYPE_EN
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| MTRR_TYPE_UNCACHEABLE),
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REG_SCRIPT_END
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};
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asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
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{
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if (IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_BOOTBLOCK_ENTRY))
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light_sd_led();
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bootblock_main_with_timestamp(base_timestamp, NULL, 0);
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}
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void bootblock_soc_early_init(void)
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{
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if (IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_SOC_EARLY_INIT_ENTRY))
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light_sd_led();
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/* Initialize the MTRRs */
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reg_script_run(mtrr_init);
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/* Initialize the controllers */
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reg_script_run_on_dev(I2CGPIO_BDF, i2c_gpio_controller_init);
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reg_script_run_on_dev(LPC_BDF, legacy_gpio_init);
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/* Enable the HSUART */
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if (IS_ENABLED(CONFIG_ENABLE_BUILTIN_HSUART0))
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reg_script_run_on_dev(HSUART0_BDF, hsuart_init);
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if (IS_ENABLED(CONFIG_ENABLE_BUILTIN_HSUART1))
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reg_script_run_on_dev(HSUART1_BDF, hsuart_init);
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if (IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_SOC_EARLY_INIT_EXIT))
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light_sd_led();
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}
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void bootblock_soc_init(void)
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{
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if (IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_SOC_INIT_ENTRY))
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light_sd_led();
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display_mtrrs();
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}
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void platform_prog_run(struct prog *prog)
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{
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/* Display the program entry point */
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printk(BIOS_SPEW, "Calling %s, 0x%p(0x%p)\n", prog->name,
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prog->entry, prog->arg);
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}
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