f7a0ba84dc
- Add an additional consistency check to romcc and fix the more obvious problems it has uncovered With this update there are no known silent failures in romcc. - Update the memory initialization code to setup all 3 of the memory sizing registers properly - In auto.c test our dynamic maximum amount of ram. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@885 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
72 lines
1.4 KiB
C
72 lines
1.4 KiB
C
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typedef __builtin_msr_t msr_t;
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static msr_t rdmsr(unsigned long index)
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{
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return __builtin_rdmsr(index);
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}
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static void uart_tx_byte(unsigned char data)
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{
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while(!(__builtin_inb(0x3f8 + 0x05) & 0x20))
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;
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__builtin_outb(data, 0x3f8 + 0x00);
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while(!(__builtin_inb(0x3f8 + 0x05) & 0x40))
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;
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}
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static void print_nibble(unsigned nibble)
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{
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unsigned char digit;
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digit = nibble + '0';
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if (digit > '9') {
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digit += 39;
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}
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uart_tx_byte(digit);
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}
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static void print_debug_hex32(unsigned int value)
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{
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print_nibble((value >> 28U) & 0x0fU);
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print_nibble((value >> 24U) & 0x0fU);
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print_nibble((value >> 20U) & 0x0fU);
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print_nibble((value >> 16U) & 0x0fU);
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print_nibble((value >> 12U) & 0x0fU);
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print_nibble((value >> 8U) & 0x0fU);
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print_nibble((value >> 4U) & 0x0fU);
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print_nibble(value & 0x0fU);
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}
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static void print_debug(const char *str)
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{
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unsigned char ch;
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while((ch = *str++) != '\0') {
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uart_tx_byte(ch);
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}
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}
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static void main(void)
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{
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unsigned long start, stop;
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msr_t msr;
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msr = rdmsr(0xC001001A);
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print_debug("TOP_MEM: ");
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print_debug_hex32(msr.hi);
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print_debug_hex32(msr.lo);
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print_debug("\r\n");
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start = 0;
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stop = msr.lo;
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print_debug("Testing DRAM : ");
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print_debug_hex32(start);
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print_debug("-");
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print_debug_hex32(stop);
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print_debug("\r\n");
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print_debug("DRAM verify: ");
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print_debug_hex32(start);
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print_debug_hex32(stop);
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}
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