d6ac209c74
The Linux kernel runtime D3 framework expects a PCIe device to have a power resource in order to be properly power-manageable. The _PR0/_PR3 values were pointing at the PEG0 Device, which is not a PowerResource, so this must have confused the RTD3 framework and RTD3 was not functional. Removing the _PR0/_PR3 fixes the problem. BUG=b:243888246 TEST=echo auto > /sys/bus/pci/devices/0000:01:00.0/power/control; sleep 10; echo on > /sys/bus/pci/devices/0000:01:00.0/power/control After this there are no longer errors seen in dmesg about failing to place the device into D0. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I83fa1e5fabd3257b097c10e7a13c9861872685ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/67212 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Cliff Huang <cliff.huang@intel.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
130 lines
2.8 KiB
Plaintext
130 lines
2.8 KiB
Plaintext
/* SPDX-License-Identifier: GPL-2.0-or-later */
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#define JT_FUNC_SUPPORT 0
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#define JT_FUNC_CAPS 1
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#define JT_FUNC_POWERCONTROL 3
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#define JT_FUNC_PLATPOLICY 4
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Method (NVJT, 2, Serialized)
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{
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Switch (ToInteger(Arg0))
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{
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Case (JT_FUNC_SUPPORT)
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{
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Return (ITOB(
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(1 << JT_FUNC_SUPPORT) |
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(1 << JT_FUNC_CAPS) |
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(1 << JT_FUNC_POWERCONTROL) |
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(1 << JT_FUNC_PLATPOLICY)))
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}
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Case (JT_FUNC_CAPS)
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{
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Return (ITOB(
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(0 << 0) | /* JTE: G-Sync NVSR Power Features Enabled */
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(1 << 0) | /* NVSE: NVSR Disabled */
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(0 << 3) | /* PPR: Panel Power Rail */
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(0 << 5) | /* SRPR: Self-Refresh Controller Power Rail */
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(0 << 6) | /* FBPR: FB Power Rail */
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(0 << 8) | /* GPR: GPU Power Rail */
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(0 << 10) | /* GCR: GC6 ROM */
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(1 << 11) | /* PTH: No SMI Handler */
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(0 << 12) | /* NOT: Supports Notify on GC6 State done */
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(1 << 13) | /* MHYB: MS Hybrid Support (deferred GC6) */
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(0 << 14) | /* RPC: Root Port Control */
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(0 << 15) | /* GC6 Version (GC6-E) */
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(0 << 17) | /* GEI: GC6 Exit ISR Support */
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(0 << 18) | /* GSW: GC6 Self Wakeup */
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(0x200 << 20))) /* MXRV: Highest Revision */
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}
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Case (JT_FUNC_POWERCONTROL)
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{
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CreateField (Arg1, 0, 3, GPC) /* GPU Power Control */
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CreateField (Arg1, 4, 1, PPC) /* Panel Power Control */
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CreateField (Arg1, 14, 2, DFGC) /* Defer GC6 enter/exit */
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CreateField (Arg1, 16, 3, GPCX) /* Deferred GC6 exit */
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/* Deferred GC6 entry/exit is requested */
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If (ToInteger(GPC) != 0 || ToInteger(DFGC) != 0)
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{
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DFEN = ToInteger(DFGC)
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DFCI = ToInteger(GPC)
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DFCO = ToInteger(GPCX)
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}
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Local0 = Buffer (4) { 0x0 }
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CreateField (Local0, 0, 3, CGCS) /* Current GC State */
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CreateField (Local0, 3, 1, CGPS) /* Current GPU power status */
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CreateField (Local0, 7, 1, CPSS) /* Current panel and SRC state */
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/* Leave early if deferred GC6 is requested */
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If (DFEN != 0)
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{
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CGCS = 1
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CGPS = 1
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Return (Local0)
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}
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Switch (ToInteger(GPC))
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{
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/* Get GCU GCx Sleep Status */
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Case (NVJT_GPC_GSS)
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{
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If (PSTA () != 0)
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{
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CGPS = 1
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CGCS = 1
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}
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Else
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{
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CGPS = 0
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CGCS = 3
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}
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}
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Case (NVJT_GPC_EGNS)
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{
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/* Enter GC6; no self-refresh */
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GC6I ()
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CPSS = 1
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CGCS = 0
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}
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Case (NVJT_GPC_EGIS)
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{
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/* Enter GC6; enable self-refresh */
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GC6I ()
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If (ToInteger (PPC) == 0)
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{
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CPSS = 0
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}
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CGCS = 0
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}
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Case (NVJT_GPS_XGXS)
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{
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/* Exit GC6; stop self-refresh */
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GC6O ()
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CGCS = 1
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CGPS = 1
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If (ToInteger (PPC) != 0)
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{
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CPSS = 0
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}
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}
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Case (NVJT_GPS_XGIS)
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{
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/* Exit GC6 for self-refresh */
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GC6O ()
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CGCS = 1
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CGPS = 1
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If (ToInteger (PPC) != 0)
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{
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CPSS = 0
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}
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}
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}
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Return (Local0)
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}
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}
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Return (NV_ERROR_UNSUPPORTED)
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}
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