Kyösti Mälkki d71cfd2041 VIA C7 NANO: Fix early MTRR setting ...

It would not be possible to set MTRR for range 1MiB to 4MiB.
Our RAMTOP is power of 2 and enabling cache for bottom
1MiB should cause no problems.

Change-Id: I3619bc25be60f42b68615bfcdf36f02d66796e02
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15238
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

2016-06-20 18:43:30 +02:00

..

acpi

acpi/: add missing license header

2016-01-14 22:52:11 +01:00

arch

Move definitions of HIGH_MEMORY_SAVE

2016-06-17 00:19:08 +02:00

commonlib

commonlib/lz4: Avoid unaligned memory access on RISC-V

2016-05-31 21:07:03 +02:00

console

console/post: be explicit about conditional cmos_post_log() compiling

2016-05-25 18:04:11 +02:00

cpu

VIA C7 NANO: Fix early MTRR setting

2016-06-20 18:43:30 +02:00

device

device: i2c: Add support for I2C bus operations

2016-06-09 17:05:40 +02:00

drivers

Fix some cbmem.h includes

2016-06-17 00:18:28 +02:00

ec

chromeec: Move EC image hash to separate file in CBFS

2016-06-03 17:24:26 +02:00

include

intel: Fix romstage main() with asmlinkage

2016-06-18 20:02:26 +02:00

lib

lib: Build reg_script for bootblock

2016-06-09 17:43:53 +02:00

mainboard

emulation/qemu-i440fx qemu-q35: Asmlinkage for romstage main()

2016-06-18 20:05:01 +02:00

northbridge

intel/model_206ax: Move platform specific defines

2016-06-17 00:22:10 +02:00

soc

intel/broadwell: Remove old USBDEBUG backup store in CAR

2016-06-19 05:21:50 +02:00

southbridge

drivers/lenovo: Add hybrid graphics driver

2016-06-01 23:22:01 +02:00

superio

sio/winbond/w83667hg-a: Add pinmux defines for UART B

2016-05-29 19:34:54 +02:00

vendorcode

Kconfig: Set VBOOT_OPROM_MATTERS for relevant non-x86 devices

2016-06-12 12:11:08 +02:00

Kconfig

Define RAMTOP for x86 only

2016-06-17 00:17:53 +02:00