d84ace50e3
Change the order of enabling EC and GPE wake sources, so it comes more obvious we can use existing chromeec handlers without changes. Change-Id: I5a10afa2b816dc8c01074be68a63114ee027c1e2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74604 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
61 lines
1.4 KiB
C
61 lines
1.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpi.h>
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#include <console/console.h>
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#include <cpu/x86/smm.h>
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#include <ec/google/chromeec/ec.h>
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#include <ec/google/chromeec/smm.h>
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#include "ec.h"
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#include <soc/pm.h>
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/* The wake gpio is SUS_GPIO[0]. */
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#define WAKE_GPIO_EN SUS_GPIO_EN0
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/* The entire 32-bit ALT_GPIO_SMI register is passed as a parameter. Note, that
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* this includes the enable bits in the lower 16 bits. */
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void mainboard_smi_gpi(uint32_t alt_gpio_smi)
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{
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if (alt_gpio_smi & (1 << EC_SMI_GPI))
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chromeec_smi_process_events();
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}
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void mainboard_smi_sleep(uint8_t slp_typ)
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{
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/* Disable USB charging if required */
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chromeec_set_usb_charge_mode(slp_typ);
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switch (slp_typ) {
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case ACPI_S3:
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/* Enable wake pin in GPE block. */
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enable_gpe(WAKE_GPIO_EN);
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break;
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}
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switch (slp_typ) {
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case ACPI_S3:
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/* Enable wake events */
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google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS);
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break;
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case ACPI_S5:
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/* Enable wake events */
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google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS);
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break;
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}
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/* Disable SCI and SMI events */
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google_chromeec_set_smi_mask(0);
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google_chromeec_set_sci_mask(0);
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/* Clear pending events that may trigger immediate wake */
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while (google_chromeec_get_event() != EC_HOST_EVENT_NONE)
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;
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}
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int mainboard_smi_apmc(uint8_t apmc)
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{
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chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, MAINBOARD_EC_SMI_EVENTS);
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return 0;
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}
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