d9ad49c250
Rework Kconfig file that each variant has its own config option with their specific selects / configuration and move common selects to `BOARD_INTEL_ADLRVP_COMMON`, which is used as base for each variant. Also, move selects from Kconfig.name to Kconfig that the configuration is at one place and not distributed over two files. Built each variant with `BUILD_TIMELESS=1` and all generated coreboot.rom files remain identical. Excluded the .config file by disabling `INCLUDE_CONFIG_FILE` to make this reproducible. Change-Id: If68c118f22579cc0a3db570119798f0f535f9804 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56221 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
143 lines
3.7 KiB
Plaintext
143 lines
3.7 KiB
Plaintext
config BOARD_INTEL_ADLRVP_COMMON
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def_bool n
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select BOARD_ROMSIZE_KB_32768
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select DRIVERS_I2C_GENERIC
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select DRIVERS_I2C_HID
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select DRIVERS_I2C_MAX98373
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select DRIVERS_INTEL_DPTF
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select DRIVERS_INTEL_MIPI_CAMERA
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select DRIVERS_INTEL_SOUNDWIRE
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select DRIVERS_SOUNDWIRE_ALC711
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select DRIVERS_SPI_ACPI
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select DRIVERS_USB_ACPI
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select HAVE_SPD_IN_CBFS
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select MAINBOARD_HAS_CHROMEOS
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select SOC_INTEL_ALDERLAKE
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select SOC_INTEL_COMMON_BLOCK_IPU
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select SOC_INTEL_CSE_LITE_SKU
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select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
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config BOARD_INTEL_ADLRVP_P
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select BOARD_INTEL_ADLRVP_COMMON
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select DRIVERS_UART_8250IO
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select MAINBOARD_USES_IFD_EC_REGION
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config BOARD_INTEL_ADLRVP_P_EXT_EC
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select BOARD_INTEL_ADLRVP_COMMON
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select DRIVERS_INTEL_PMC
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select INTEL_LPSS_UART_FOR_CONSOLE
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config BOARD_INTEL_ADLRVP_P_MCHP
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select BOARD_INTEL_ADLRVP_COMMON
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select DRIVERS_INTEL_MIPI_CAMERA
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select DRIVERS_INTEL_PMC
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select EC_GOOGLE_CHROMEEC_ACPI_MEMMAP
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select EC_GOOGLE_CHROMEEC_MEC
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select INTEL_LPSS_UART_FOR_CONSOLE
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select SOC_INTEL_COMMON_BLOCK_IPU
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config BOARD_INTEL_ADLRVP_M
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select BOARD_INTEL_ADLRVP_COMMON
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select DRIVERS_UART_8250IO
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select MAINBOARD_USES_IFD_EC_REGION
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select SOC_INTEL_ALDERLAKE_PCH_M
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config BOARD_INTEL_ADLRVP_M_EXT_EC
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select BOARD_INTEL_ADLRVP_COMMON
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select DRIVERS_INTEL_PMC
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select FW_CONFIG
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select FW_CONFIG_SOURCE_CHROMEEC_CBI
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select INTEL_LPSS_UART_FOR_CONSOLE
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select MAINBOARD_HAS_SPI_TPM_CR50
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select MAINBOARD_HAS_TPM2
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select SOC_INTEL_ALDERLAKE_PCH_M
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select SPI_TPM
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if BOARD_INTEL_ADLRVP_COMMON
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config CHROMEOS
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select GBB_FLAG_FORCE_DEV_SWITCH_ON
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select GBB_FLAG_FORCE_DEV_BOOT_USB
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select GBB_FLAG_FORCE_DEV_BOOT_ALTFW
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select GBB_FLAG_FORCE_MANUAL_RECOVERY
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select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC
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select HAS_RECOVERY_MRC_CACHE
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config MAINBOARD_DIR
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default "intel/adlrvp"
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config VARIANT_DIR
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default "adlrvp_p" if BOARD_INTEL_ADLRVP_P
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default "adlrvp_p_ext_ec" if BOARD_INTEL_ADLRVP_P_EXT_EC
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default "adlrvp_p_mchp" if BOARD_INTEL_ADLRVP_P_MCHP
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default "adlrvp_m" if BOARD_INTEL_ADLRVP_M
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default "adlrvp_m_ext_ec" if BOARD_INTEL_ADLRVP_M_EXT_EC
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config GBB_HWID
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string
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depends on CHROMEOS
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default "ADLRVPM" if BOARD_INTEL_ADLRVP_M || BOARD_INTEL_ADLRVP_M_EXT_EC
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default "ADLRVPP"
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config MAINBOARD_PART_NUMBER
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default "Alder Lake Client Platform"
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config MAINBOARD_VENDOR
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string
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default "Intel Corporation"
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config MAINBOARD_FAMILY
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string
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default "Intel_adlrvp"
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config DEVICETREE
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default "devicetree_m.cb" if BOARD_INTEL_ADLRVP_M || BOARD_INTEL_ADLRVP_M_EXT_EC
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default "devicetree.cb"
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config OVERRIDE_DEVICETREE
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default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
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config DIMM_SPD_SIZE
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default 512
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choice
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prompt "ON BOARD EC"
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default ADL_INTEL_EC if BOARD_INTEL_ADLRVP_P || BOARD_INTEL_ADLRVP_M
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default ADL_CHROME_EC if BOARD_INTEL_ADLRVP_P_EXT_EC || BOARD_INTEL_ADLRVP_M_EXT_EC || BOARD_INTEL_ADLRVP_P_MCHP
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help
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This option allows you to select the on board EC to use.
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Select whether the board has Intel EC or Chrome EC
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config ADL_CHROME_EC
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bool "Chrome EC"
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select EC_GOOGLE_CHROMEEC
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select EC_GOOGLE_CHROMEEC_ESPI
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select EC_GOOGLE_CHROMEEC_BOARDID
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select EC_ACPI
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select EC_GOOGLE_CHROMEEC_LPC
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config ADL_INTEL_EC
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bool "Intel EC"
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select EC_ACPI
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endchoice
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config VBOOT
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select VBOOT_LID_SWITCH
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select VBOOT_MOCK_SECDATA if BOARD_INTEL_ADLRVP_P_EXT_EC
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select EC_GOOGLE_CHROMEEC_SWITCHES if ADL_CHROME_EC
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select VBOOT_EARLY_EC_SYNC if BOARD_INTEL_ADLRVP_M_EXT_EC
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config UART_FOR_CONSOLE
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int
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default 0
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config DRIVER_TPM_SPI_BUS
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default 0x2 if BOARD_INTEL_ADLRVP_M_EXT_EC
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config TPM_TIS_ACPI_INTERRUPT
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int
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default 67 if BOARD_INTEL_ADLRVP_M_EXT_EC # GPE0_DW2_3 (GPP_E3)
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endif
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