Felix Held 8f57fa5091 vc/google/chromeec/acpi: write OIPG in DECLARE_NO_CROS_GPIOS case
When a mainboard selects ACPI_SOC_NVS and CHROMEOS, CHROMEOS_NVS will be
selected. This causes vc/google/chromeec/acpi/chromeos.asl to be
included in the DSDT and chromeos_acpi_gpio_generate to be called when
generating the coreboot SSDT. When a mainboard also uses
DECLARE_NO_CROS_GPIOS(), this will cause variant_cros_gpio.count to be 0
and variant_cros_gpio.gpios to be NULL. chromeos_acpi_gpio_generate only
checked if the GPIO table was non-NULL, which caused the function to
exit early and not generate the OIPG package which causes the kernel to
complain about referencing the non-existing OIPG package. To avoid this,
only exit in the GPIO table pointer being NULL case if the number of
GPIOs is non-0.

TEST=Error about missing OIPG ACPI object in dmesg disappears on birman.

Before:

[    0.241339] chromeos_acpi: registering CHSW 0
[    0.241468] ACPI BIOS Error (bug): Could not resolve symbol [\CRHW.GPIO.OIPG], AE_NOT_FOUND (20220331/psargs-330)
[    0.241703] ACPI Error: Aborting method \CRHW.GPIO due to previous error (AE_NOT_FOUND) (20220331/psparse-531)
[    0.241933] chromeos_acpi: failed to retrieve GPIO (5)
[    0.242011] chromeos_acpi: registering VBNV 0
[    0.242113] chromeos_acpi: registering VBNV 1
[    0.242284] chromeos_acpi: truncating buffer from 3072 to 1336
[    0.242462] chromeos_acpi: installed

With the patch applied:

[    0.242580] chromeos_acpi: registering CHSW 0
[    0.242714] chromeos_acpi: registering VBNV 0
[    0.242817] chromeos_acpi: registering VBNV 1
[    0.242990] chromeos_acpi: truncating buffer from 3072 to 1336
[    0.243249] chromeos_acpi: installed

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Ie340003afb718b1454c2da4a479882b71714c3c7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74375
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-14 14:48:36 +00:00
..
2023-02-07 04:37:31 +00:00
2022-10-20 14:52:41 +00:00

The files in the coreboot src/vendorcode subdirectory are supplied by various hardware and software vendors to support their platforms. While these directories and files are a part of the coreboot project, their licenses, coding styles, and maintenance may be significantly different than the rest of the coreboot codebase.

By contributing these directories and files to the coreboot codebase, the authors and copyright holders have agreed to the use and modification of these files by the coreboot community, however the final ownership and responsibility still remains with the company that contributed the files.

The ideal goal would be to properly integrate these files into coreboot proper. But such undertakings should be coordinated with the owners. Community modification should in general be limited to fixing issues and adding functionality.

Licenses for the files were determined by the copyright holder when the files were contributed. All files here must have an open source license compatible with coreboot's GPL v2.