db2e11841a
Until now, the buildOpts.c files were primarily made out of copy-pasted AGESA options, commented-out definitions and several useless comments; that is, the materialization of technical debt in GCC-parsable form... Until now. It is assumed that the boards in the tree still boot. So, by comparing their settings, we can extract saner defaults to place into AGESA. Many of the settings were common across all boards of the same family, so we promote those values to default settings. In some cases flipping a flag was required, so the macros to alter that option had to be adapted as well. Since those AGESA versions are expected to never receive updates, it should not be a problem to change their files to suit our needs. As a result, all but two buildOpts.c files now have less than 100 lines. AGESA f14 boards need less than 50 lines, and f15tn/f16kb just require about 60 or 70 lines in those files. Hopefully, this will make porting more mainboards using AGESA f14/f15tn/f16kb a substantially easier task. TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb mainboards result in identical coreboot binaries. Change-Id: Ife1ca5177d85441b9a7b24d64d7fcbabde6e0409 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mike Banon <mikebdp2@gmail.com>
62 lines
2.2 KiB
C
62 lines
2.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <vendorcode/amd/agesa/f15tn/AGESA.h>
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/* Include the files that instantiate the configuration definitions. */
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#include <vendorcode/amd/agesa/f15tn/Include/AdvancedApi.h>
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#include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h>
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#include <vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatures.h>
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#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h>
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/* AGESA nonsense: the next two headers depend on heapManager.h */
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#include <vendorcode/amd/agesa/f15tn/Proc/Common/CreateStruct.h>
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#include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEarlyInit.h>
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/* These tables are optional and may be used to adjust memory timing settings */
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#include <vendorcode/amd/agesa/f15tn/Proc/Mem/mm.h>
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#include <vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h>
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/* Select the CPU family */
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#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE
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/* Select the CPU socket type */
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#define INSTALL_FM2_SOCKET_SUPPORT TRUE
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//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE
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#define BLDOPT_REMOVE_SODIMMS_SUPPORT TRUE
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#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE
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#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE
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#define BLDOPT_REMOVE_ECC_SUPPORT TRUE
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#define BLDOPT_REMOVE_SRAT FALSE
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#define BLDOPT_REMOVE_WHEA FALSE
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#define BLDOPT_REMOVE_CRAT TRUE
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/* Build configuration values here. */
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#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE
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#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE
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#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE
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#define BLDCFG_MEMORY_SODIMM_CAPABLE FALSE
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#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE
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#define BLDCFG_MEMORY_CLOCK_SELECT DDR1600_FREQUENCY
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#define BLDCFG_ENABLE_ECC_FEATURE FALSE
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#define BLDCFG_ECC_SYNC_FLOOD FALSE
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#define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED
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#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000 /* (0x2000 << 16) = 512M */
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#define BLDCFG_IOMMU_SUPPORT TRUE
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#define BLDCFG_CFG_GNB_HD_AUDIO TRUE
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/* Customized OEM build configurations for FCH component */
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#define BLDCFG_FCH_GPP_LINK_CONFIG PortA1B1C1D1
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#define BLDCFG_FCH_GPP_PORT0_PRESENT TRUE
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#define BLDCFG_FCH_GPP_PORT1_PRESENT TRUE
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GPIO_CONTROL f2a85_m_gpio[] = {
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{-1}
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};
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#define BLDCFG_FCH_GPIO_CONTROL_LIST (f2a85_m_gpio)
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/* Moving this include up will break AGESA. */
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#include <PlatformInstall.h>
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