db3e2f0931
Include clock.c in the appropriate coreboot stages, modify the code to build cleanly. Use proper pointer cast in .h files. BUG=chrome-os-partner:27784 TEST='emerge-storm coreboot' still succeeds Original-Change-Id: I227c871b17e571f6a1db3ada3821dbb1ee884e59 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/196407 (cherry picked from commit 75decceccd97298974891bb98b796eccfe11f46c) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I7d44464d4ca8153e84407fc05a25e2e79e74901e Reviewed-on: http://review.coreboot.org/7271 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
100 lines
3.9 KiB
C
100 lines
3.9 KiB
C
/*
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* Copyright (c) 2012 - 2013 The Linux Foundation. All rights reserved.
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*
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* Copyright (c) 2008, Google Inc.
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* All rights reserved.
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*
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* Copyright (c) 2009-2012, Code Aurora Forum. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Google, Inc. nor the names of its contributors
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* may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef __SOC_QUALCOMM_IPQ806X_IOMAP_H_
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#define __SOC_QUALCOMM_IPQ806X_IOMAP_H_
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/* Typecast to allow integers being passed as address
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This needs to be included because vendor code is not compliant with our
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macros for read/write. Hence, special macros for readl_i and writel_i are
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included to do this in one place for all occurrences in vendor code
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*/
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#define readl_i(a) read32((const void *)(a))
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#define writel_i(v,a) write32(v,(void *)a)
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#include <arch/io.h>
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#include <cdp.h>
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#define MSM_CLK_CTL_BASE 0x00900000
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#define MSM_TMR_BASE 0x0200A000
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#define MSM_GPT_BASE (MSM_TMR_BASE + 0x04)
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#define MSM_DGT_BASE (MSM_TMR_BASE + 0x24)
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#define GPT_REG(off) ((void *)(MSM_GPT_BASE + (off)))
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#define DGT_REG(off) (MSM_DGT_BASE + (off))
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#define APCS_WDT0_EN (MSM_TMR_BASE + 0x0040)
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#define APCS_WDT0_RST (MSM_TMR_BASE + 0x0038)
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#define APCS_WDT0_BARK_TIME (MSM_TMR_BASE + 0x004C)
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#define APCS_WDT0_BITE_TIME (MSM_TMR_BASE + 0x005C)
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#define APCS_WDT0_CPU0_WDOG_EXPIRED_ENABLE (MSM_CLK_CTL_BASE + 0x3820)
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#define GPT_MATCH_VAL GPT_REG(0x0000)
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#define GPT_COUNT_VAL GPT_REG(0x0004)
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#define GPT_ENABLE GPT_REG(0x0008)
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#define GPT_CLEAR GPT_REG(0x000C)
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#define GPT1_MATCH_VAL GPT_REG(0x00010)
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#define GPT1_COUNT_VAL GPT_REG(0x00014)
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#define GPT1_ENABLE GPT_REG(0x00018)
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#define GPT1_CLEAR GPT_REG(0x0001C)
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#define DGT_MATCH_VAL DGT_REG(0x0000)
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#define DGT_COUNT_VAL DGT_REG(0x0004)
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#define DGT_ENABLE DGT_REG(0x0008)
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#define DGT_CLEAR DGT_REG(0x000C)
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#define DGT_CLK_CTL DGT_REG(0x0010)
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#define TLMM_BASE_ADDR 0x00800000
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#define GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + 0x1000 + (x)*0x10)
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#define GPIO_IN_OUT_ADDR(x) (TLMM_BASE_ADDR + 0x1004 + (x)*0x10)
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#define GSBI_1 1
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#define GSBI_2 2
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#define GSBI_4 4
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#define GSBI_2 2
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#define UART1_DM_BASE 0x12450000
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#define UART_GSBI1_BASE 0x12440000
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#define UART2_DM_BASE 0x12490000
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#define UART_GSBI2_BASE 0x12480000
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#define UART4_DM_BASE 0x16340000
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#define UART_GSBI4_BASE 0x16300000
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#define UART2_DM_BASE 0x12490000
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#define UART_GSBI2_BASE 0x12480000
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#endif // __SOC_QUALCOMM_IPQ806X_IOMAP_H_
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