db44be9405
msr set in northbridge that conflicted with the cpubug support. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2218 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
365 lines
7.4 KiB
C
365 lines
7.4 KiB
C
#include <cpu/amd/model_gx2/gx2def.h>
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void
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cpubug(void){
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msr_t msr;
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int rev;
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msr = rdmsr(GLCP_CHIP_REVID);
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rev = msr.lo & 0xff;
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if (rev < 0x20) {
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printk_error("%s: rev < 0x20! bailing!\n");
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return;
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}
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switch(rev)
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{
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case 0x20:
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pcideadlock();
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eng1398();
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bug752();
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break;
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case 0x22:
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pcideadlock();
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eng1398();
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eng2900();
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bug 118339();
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break;
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case 0x22:
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case 0x30:
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break;
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default:
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printk_error("unknown rev %x, bailing\n", rev);
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return;
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}
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bug784();
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bug118253();
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disablememoryreadorder();
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}
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#if 0
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void
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bug645(void){
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msr_t msr;
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rdmsr(CPU_ID_CONFIG);
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msr.whatever |= ID_CONFIG_SERIAL_SET;
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wrmsr(msr);
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}
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void
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bug573(void){
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msr_t msr;
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msr = rdmsr(MC_GLD_MSR_PM);
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msr.eax &= 0xfff3;
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wrmsr(MC_GLD_MSR_PM);
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}
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static void
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pcideadlock(void){
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msr_t msr;
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msr = rdmsr(CPU_DM_CONFIG0);
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msr.hi &= ~(7<<DM_CONFIG0_UPPER_WSREQ_SHIFT);
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msr.hi |= (2<<DM_CONFIG0_UPPER_WSREQ_SHIFT);
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msr.lo |= DM_CONFIG0_LOWER_MISSER_SET;
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wrmsr(CPU_DM_CONFIG0, msr);
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msr = rdmsr(CPU_IM_CONFIG);
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msr.lo |= IM_CONFIG_LOWER_QWT_SET; /* interlock instruction fetches to WS regions with data accesses.
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* This prevents in instruction fetch from going out to PCI if the
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* data side is about to make a request.
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*/
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wrmsr(CPU_IM_CONFIG, msr);
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/* write serialize memory hole to PCI. Need to to unWS when something is shadowed regardless of cachablility.*/
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msr.lo = 0x021212121;
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msr.hi = 0x021212121
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wrmsr( CPU_RCONF_A0_BF, msr);
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wrmsr( CPU_RCONF_C0_DF, msr);
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wrmsr( CPU_RCONF_E0_FF, msr);
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}
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;**************************************************************************
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;*
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;* CPUbug784
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;*
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;* Bugtool #784 + #792
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;*
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;* Fix CPUID instructions for < 3.0 CPUs
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;*
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;* Entry:
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;* Exit:
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;* Modified:
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;*
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;**************************************************************************
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void cpubug784(void){
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static char *name = "Geode by NSC";
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/* we'll do this the stupid way, for now, but that's the string they want. NO ONE KNOWS why you
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* would do this -- the OS can figure this type of stuff out!
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*/
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msr = rdmsr(0x3006);
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msr.hi = 0x646f6547;
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wrmsr(0x3006, msr);
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msr = rdmsr(0x3007);
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msr.hi = 0x79622065;
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msr.lo = 0x43534e20;
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wrmsr(0x3007, msr);
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msr = rdmsr(0x3002);
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wrmsr(*0x3008, msr);
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; More CPUID to match AMD better. #792
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msr = rdmsr(0x3009);
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msr.hi = 0x0C0C0A13D;
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msr.lo = 0x00000000;
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wrmsr(0x3009, msr);
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}
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/* cpubug 1398: enable MC if we KNOW we have DDR*/
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void
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eng1398(void){
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msr_t msr;
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msr = rdmsr(MSR_GLCP+0x17);
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if ((msr.lo & 0xff) < CPU_REV_2_0) {
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msr = rdmsr(GLCP_SYS_RSTPLL);
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i if (msr.lo & (1<<RSTPPL_LOWER_SDRMODE_SHIFT))
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return;
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}
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/* no bios to check, we just go for it? */
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msr = rdmsr(MC_GLD_MSR_PM);
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msr.lo |= 3; /* enable MC clock gating.*/
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wrmsr(MC_GLD_MSR_PM, msr);
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}
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void
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eng2900{void){
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printk_err(" NOT DOING eng2900: only shown to be a windows problem\n");
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#if 0
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;**************************************************************************
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;*
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;* CPUbugIAENG2900
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;*
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;* Clear Quest IAENG00002900, VSS 118.150
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;*
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;* BTB issue causes blue screen in windows.
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;*
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;* Entry:
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;* Exit:
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;* Modified:
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;*
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;**************************************************************************
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CPUbugIAENG2900 PROC NEAR PUBLIC
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pushad
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; Clear bit 43, disables the sysenter/sysexit in CPUID3
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mov ecx, 3003h
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RDMSR
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and edx, 0FFFFF7FFh
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WRMSR
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mov cx, TOKEN_BTB_2900_SWAPSIF_ENABLE
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NOSTACK bx, GetNVRAMValueBX
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cmp ax, TVALUE_ENABLE
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jne bug2900exit
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;Disable enable_actions in DIAGCTL while setting up GLCP
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mov ecx, MSR_GLCP + 005fh
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xor edx, edx
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xor eax, eax
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WRMSR
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;Changing DBGCLKCTL register to GeodeLink
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mov ecx, MSR_GLCP + 0016h
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xor edx, edx
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xor eax, eax
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WRMSR
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mov ecx, MSR_GLCP + 0016h
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xor edx, edx
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mov eax, 02h
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WRMSR
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;The code below sets up the RedCloud to stall for 4 GeodeLink clocks when CPU is snooped.
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;Because setting XSTATE to 0 overrides any other XSTATE action, the code will always
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;stall for 4 GeodeLink clocks after a snoop request goes away even if it occured a clock or two
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;later than a different snoop; the stall signal will never 'glitch high' for
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;only one or two CPU clocks with this code.
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;Send mb0 port 3 requests to upper GeodeLink diag bits [63:32]
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mov ecx, MSR_GLIU0 + 2005h
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xor edx, edx
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mov eax, 80338041h
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WRMSR
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;set5m watches request ready from mb0 to CPU (snoop)
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mov ecx, MSR_GLCP + 0045h
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mov edx, 5ad68000h
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xor eax, eax
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WRMSR
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;SET4M will be high when state is idle (XSTATE=11)
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mov ecx, MSR_GLCP + 0044h
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xor edx, edx
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mov eax, 0140h
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WRMSR
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;SET5n to watch for processor stalled state
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mov ecx, MSR_GLCP + 004Dh
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mov edx, 2000h
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xor eax, eax
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WRMSR
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;Writing action number 13: XSTATE=0 to occur when CPU is snooped unless we're stalled
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mov ecx, MSR_GLCP + 0075h
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xor edx, edx
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mov eax, 00400000h
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WRMSR
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;Writing action number 11: inc XSTATE every GeodeLink clock unless we're idle
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mov ecx, MSR_GLCP + 0073h
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xor edx, edx
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mov eax, 30000h
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WRMSR
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;Writing action number 5: STALL_CPU_PIPE when exitting idle state or not in idle state
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mov ecx, MSR_GLCP + 006Dh
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xor edx, edx
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mov eax, 00430000h
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WRMSR
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;Writing DIAGCTL Register to enable the stall action and to let set5m watch the upper GeodeLink diag bits.
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mov ecx, MSR_GLCP + 005fh
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xor edx, edx
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mov eax, 80004000h
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WRMSR
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bug2900exit:
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popad
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ret
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CPUbugIAENG2900 ENDP
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#endif
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}
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void eng118253(void){
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msr_t msr;
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msr = rdmsr(GLPCI_SPARE);
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msr.lo &= ~GLPCI_SPARE_LOWER_PPC_SET;
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wrmsr(GLPCI_SPARE, msr);
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}
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void
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bug118339(void) {
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printk_err("This is OPTIONAL BIOS-ENABLED ... ignore for now\n");
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#if 0
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PROC NEAR PUBLIC
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pushad
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mov cx, TOKEN_VGTEAR_118339_SWAPSIF_ENABLE
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NOSTACK bx, GetNVRAMValueBX
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cmp ax, TVALUE_ENABLE
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jne bug118339exit
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;Disable enable_actions in DIAGCTL while setting up GLCP
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mov ecx, MSR_GLCP + 005fh
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xor edx, edx
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xor eax, eax
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WRMSR
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; SET2M fires if VG pri is odd (3, not 2) and Ystate=0
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mov ecx, MSR_GLCP + 042h
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; mov edx, 2d6b8000h
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mov edx, 596b8000h
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mov eax, 00000a00h
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WRMSR
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; SET3M fires if MBUS changed and VG pri is odd
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mov ecx, MSR_GLCP + 043h
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mov edx, 596b8040h
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xor eax, eax
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WRMSR
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; Put VG request data on lower diag bus
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mov ecx, MSR_GLIU0 + 2005h
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xor edx, edx
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mov eax, 80338041h
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WRMSR
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; Increment Y state if SET3M if true
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mov ecx, MSR_GLCP + 074h
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xor edx, edx
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mov eax, 0000c000h
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WRMSR
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; Set up MBUS action to PRI=3 read of MBIU
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mov ecx, MSR_GLCP + 020h
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mov edx, 0000d863h
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mov eax, 20002000h
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WRMSR
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; Trigger MBUS action if VG=pri3 and Y=0, this blocks most PCI
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mov ecx, MSR_GLCP + 071h
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xor edx, edx
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mov eax, 00000c00h
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WRMSR
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;Writing DIAGCTL
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mov ecx, MSR_GLCP + 005fh
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xor edx, edx
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mov eax, 80004000h
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WRMSR
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; Code to enable FS2 even when BTB and VGTEAR SWAPSiFs are enabled
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; As per Todd Roberts in PBz1094 and PBz1095
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; Moved from CPUREG to CPUBUG per Tom Sylla
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mov ecx, 04C000042h ; GLCP SETMCTL Register
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rdmsr
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or edx, 8 ; Bit 35 = MCP_IN
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wrmsr
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bug118339exit:
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popad
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ret
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CPUbug118339 ENDP
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#endif
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}
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/****************************************************************************/
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/***/
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/** DisableMemoryReorder*/
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/***/
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/** PBZ 3659:*/
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/** The MC reordered transactions incorrectly and breaks coherency.*/
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/** Disable reording and take a potential performance hit.*/
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/** This is safe to do here and not in MC init since there is nothing*/
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/** to maintain coherency with and the cache is not enabled yet.*/
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/***/
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/***/
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/** Entry:*/
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/** Exit:*/
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/** Modified:*/
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/***/
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/****************************************************************************/
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void
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DisableMemoryReorder(void) {
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msr_t msr;
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msr = rdmsr(MC_CF8F_DATA);
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msr.hi |= CF8F_UPPER_REORDER_DIS_SET);
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wrmsr(MC_CF8F_DATA, msr);
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}
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