b4523bb691
The interval used to be about 55 ms which is excessively long. Coreboot only waits for 2 ms and gets a reasonable answer. That should be good enough for us as well. Change-Id: I4d4e8b25b6ba540c9e9839ed0bbaa1f04f67cce1 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://review.coreboot.org/2520 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
127 lines
3.5 KiB
C
127 lines
3.5 KiB
C
/*
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* This file is part of the libpayload project.
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*
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* Copyright (C) 2008 Advanced Micro Devices, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/**
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* @file i386/timer.c
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* i386 specific timer routines
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*/
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#include <libpayload.h>
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#include <arch/rdtsc.h>
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/**
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* @ingroup arch
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* Global variable containing the speed of the processor in KHz.
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*/
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u32 cpu_khz;
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/**
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* Calculate the speed of the processor for use in delays.
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*
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* @return The CPU speed in kHz.
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*/
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unsigned int get_cpu_speed(void)
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{
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unsigned long long start, end;
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const uint32_t clock_rate = 1193182; // 1.193182 MHz
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const uint16_t interval = (2 * clock_rate) / 1000; // 2 ms
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/* Set up the PPC port - disable the speaker, enable the T2 gate. */
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outb((inb(0x61) & ~0x02) | 0x01, 0x61);
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/* Set the PIT to Mode 0, counter 2, word access. */
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outb(0xB0, 0x43);
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/* Load the interval into the counter. */
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outb(interval & 0xff, 0x42);
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outb((interval >> 8) & 0xff, 0x42);
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/* Read the number of ticks during the period. */
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start = rdtsc();
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while (!(inb(0x61) & 0x20)) ;
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end = rdtsc();
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/*
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* The number of milliseconds for a period is
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* clock_rate / (interval * 1000). Multiply that by the number of
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* measured clocks to get the kHz value.
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*/
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cpu_khz = (end - start) * clock_rate / (1000 * interval);
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return cpu_khz;
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}
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static inline void _delay(unsigned long long delta)
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{
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unsigned long long timeout = rdtsc() + delta;
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while (rdtsc() < timeout) ;
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}
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/**
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* Delay for a specified number of nanoseconds.
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*
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* @param n Number of nanoseconds to delay for.
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*/
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void ndelay(unsigned int n)
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{
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_delay((unsigned long long)n * cpu_khz / 1000000);
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}
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/**
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* Delay for a specified number of microseconds.
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*
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* @param n Number of microseconds to delay for.
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*/
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void udelay(unsigned int n)
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{
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_delay((unsigned long long)n * cpu_khz / 1000);
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}
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/**
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* Delay for a specified number of milliseconds.
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*
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* @param m Number of milliseconds to delay for.
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*/
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void mdelay(unsigned int m)
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{
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_delay((unsigned long long)m * cpu_khz);
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}
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/**
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* Delay for a specified number of seconds.
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*
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* @param s Number of seconds to delay for.
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*/
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void delay(unsigned int s)
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{
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int i;
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for (i=0; i<1000; i++)
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_delay((unsigned long long)s * cpu_khz);
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}
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