dc006c1db4
The Exynos GPIO code has three different APIs that, unfortunately, were widely used throughout the code base. This patch is cleaning up the mess. Change-Id: I09ccc7819fb892dbace9693c786dacc62f3f8eac Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3643 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
299 lines
7.5 KiB
C
299 lines
7.5 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 Samsung Electronics
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <assert.h>
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#include "gpio.h"
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#include "cpu.h"
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#include "pinmux.h"
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int exynos_pinmux_config(enum periph_id peripheral, int flags)
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{
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int i, start, count, start_ext, pin_ext, pin, drv;
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switch (peripheral) {
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case PERIPH_ID_UART0:
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case PERIPH_ID_UART1:
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case PERIPH_ID_UART2:
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case PERIPH_ID_UART3:
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switch (peripheral) {
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default:
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case PERIPH_ID_UART0:
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start = GPIO_A00; count = 4;
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break;
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case PERIPH_ID_UART1:
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start = GPIO_A04; count = 4;
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break;
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case PERIPH_ID_UART2:
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start = GPIO_A10; count = 4;
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break;
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case PERIPH_ID_UART3:
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start = GPIO_A14; count = 2;
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break;
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}
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for (i = start; i < start + count; i++) {
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gpio_set_pull(i, GPIO_PULL_NONE);
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gpio_cfg_pin(i, GPIO_FUNC(0x2));
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}
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break;
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case PERIPH_ID_SDMMC0:
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case PERIPH_ID_SDMMC1:
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case PERIPH_ID_SDMMC2:
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case PERIPH_ID_SDMMC3:
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pin = GPIO_FUNC(0x2);
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pin_ext = GPIO_FUNC(0x2);
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drv = GPIO_DRV_4X;
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switch (peripheral) {
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default:
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case PERIPH_ID_SDMMC0:
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start = GPIO_C00;
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start_ext = GPIO_C10;
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break;
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case PERIPH_ID_SDMMC1:
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start = GPIO_C20;
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start_ext = 0;
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break;
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case PERIPH_ID_SDMMC2:
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start = GPIO_C30;
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/*
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* TODO: (alim.akhtar@samsung.com)
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* add support for 8 bit mode (needs to be a per-board
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* option, so in the FDT).
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*/
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start_ext = 0;
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break;
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case PERIPH_ID_SDMMC3:
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/*
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* TODO: Need to add defintions for GPC4 before
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* enabling this.
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*/
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printk(BIOS_DEBUG, "SDMMC3 not supported yet");
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return -1;
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}
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if ((flags & PINMUX_FLAG_8BIT_MODE) && !start_ext) {
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printk(BIOS_DEBUG, "SDMMC device %d does not support 8bit mode",
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peripheral);
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return -1;
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}
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if (flags & PINMUX_FLAG_8BIT_MODE) {
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ASSERT(peripheral == PERIPH_ID_SDMMC0);
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for (i = 0; i <= 3; i++) {
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gpio_cfg_pin(start_ext + i, pin_ext);
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gpio_set_pull(start_ext + i,
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GPIO_PULL_UP);
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gpio_set_drv(start_ext + i, drv);
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}
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}
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for (i = 0; i < 2; i++) {
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gpio_cfg_pin(start + i, pin);
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gpio_set_pull(start + i, GPIO_PULL_NONE);
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gpio_set_drv(start + i, drv);
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}
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for (i = 2; i <= 6; i++) {
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gpio_cfg_pin(start + i, pin);
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gpio_set_pull(start + i, GPIO_PULL_UP);
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gpio_set_drv(start + i, drv);
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}
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break;
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case PERIPH_ID_SROMC:
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/*
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* SROM:CS1 and EBI
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*
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* GPY0[0] SROM_CSn[0]
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* GPY0[1] SROM_CSn[1](2)
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* GPY0[2] SROM_CSn[2]
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* GPY0[3] SROM_CSn[3]
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* GPY0[4] EBI_OEn(2)
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* GPY0[5] EBI_EEn(2)
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*
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* GPY1[0] EBI_BEn[0](2)
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* GPY1[1] EBI_BEn[1](2)
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* GPY1[2] SROM_WAIT(2)
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* GPY1[3] EBI_DATA_RDn(2)
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*/
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gpio_cfg_pin(GPIO_Y00 + (flags & PINMUX_FLAG_BANK),
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GPIO_FUNC(2));
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gpio_cfg_pin(GPIO_Y04, GPIO_FUNC(2));
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gpio_cfg_pin(GPIO_Y05, GPIO_FUNC(2));
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for (i = 2; i < 4; i++)
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gpio_cfg_pin(GPIO_Y10 + i, GPIO_FUNC(2));
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/*
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* EBI: 8 Addrss Lines
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*
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* GPY3[0] EBI_ADDR[0](2)
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* GPY3[1] EBI_ADDR[1](2)
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* GPY3[2] EBI_ADDR[2](2)
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* GPY3[3] EBI_ADDR[3](2)
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* GPY3[4] EBI_ADDR[4](2)
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* GPY3[5] EBI_ADDR[5](2)
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* GPY3[6] EBI_ADDR[6](2)
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* GPY3[7] EBI_ADDR[7](2)
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*
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* EBI: 16 Data Lines
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*
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* GPY5[0] EBI_DATA[0](2)
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* GPY5[1] EBI_DATA[1](2)
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* GPY5[2] EBI_DATA[2](2)
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* GPY5[3] EBI_DATA[3](2)
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* GPY5[4] EBI_DATA[4](2)
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* GPY5[5] EBI_DATA[5](2)
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* GPY5[6] EBI_DATA[6](2)
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* GPY5[7] EBI_DATA[7](2)
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*
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* GPY6[0] EBI_DATA[8](2)
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* GPY6[1] EBI_DATA[9](2)
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* GPY6[2] EBI_DATA[10](2)
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* GPY6[3] EBI_DATA[11](2)
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* GPY6[4] EBI_DATA[12](2)
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* GPY6[5] EBI_DATA[13](2)
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* GPY6[6] EBI_DATA[14](2)
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* GPY6[7] EBI_DATA[15](2)
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*/
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for (i = 0; i < 8; i++) {
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gpio_cfg_pin(GPIO_Y30 + i, GPIO_FUNC(2));
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gpio_set_pull(GPIO_Y30 + i, GPIO_PULL_UP);
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gpio_cfg_pin(GPIO_Y50 + i, GPIO_FUNC(2));
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gpio_set_pull(GPIO_Y50 + i, GPIO_PULL_UP);
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if (flags & PINMUX_FLAG_16BIT) {
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gpio_cfg_pin(GPIO_Y60 + i, GPIO_FUNC(2));
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gpio_set_pull(GPIO_Y60 + i,
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GPIO_PULL_UP);
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}
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}
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break;
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case PERIPH_ID_SPI0:
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case PERIPH_ID_SPI1:
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case PERIPH_ID_SPI2:
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case PERIPH_ID_SPI3: {
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int cfg;
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switch (peripheral) {
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default:
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case PERIPH_ID_SPI0:
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start = GPIO_A20;
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cfg = 0x2;
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break;
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case PERIPH_ID_SPI1:
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start = GPIO_A24;
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cfg = 0x2;
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break;
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case PERIPH_ID_SPI2:
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start = GPIO_B11;
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cfg = 0x5;
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break;
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case PERIPH_ID_SPI3:
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start = GPIO_E00;
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cfg = 0x2;
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break;
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}
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for (i = 0; i < 4; i++)
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gpio_cfg_pin(start + i, GPIO_FUNC(cfg));
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break;
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}
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case PERIPH_ID_SPI4:
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for (i = 0; i < 2; i++)
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gpio_cfg_pin(GPIO_F02 + i, GPIO_FUNC(0x4));
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for (i = 2; i < 4; i++)
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gpio_cfg_pin(GPIO_E02 + i, GPIO_FUNC(0x4));
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break;
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case PERIPH_ID_BACKLIGHT:
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gpio_cfg_pin(GPIO_B20, GPIO_OUTPUT);
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gpio_set_value(GPIO_B20, 1);
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break;
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case PERIPH_ID_LCD:
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gpio_cfg_pin(GPIO_Y25, GPIO_OUTPUT);
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gpio_set_value(GPIO_Y25, 1);
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gpio_cfg_pin(GPIO_X15, GPIO_OUTPUT);
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gpio_set_value(GPIO_X15, 1);
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gpio_cfg_pin(GPIO_X30, GPIO_OUTPUT);
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gpio_set_value(GPIO_X30, 1);
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break;
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case PERIPH_ID_I2C0:
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gpio_cfg_pin(GPIO_B30, GPIO_FUNC(0x2));
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gpio_cfg_pin(GPIO_B31, GPIO_FUNC(0x2));
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gpio_set_pull(GPIO_B30, GPIO_PULL_NONE);
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gpio_set_pull(GPIO_B31, GPIO_PULL_NONE);
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break;
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case PERIPH_ID_I2C1:
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gpio_cfg_pin(GPIO_B32, GPIO_FUNC(0x2));
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gpio_cfg_pin(GPIO_B33, GPIO_FUNC(0x2));
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gpio_set_pull(GPIO_B32, GPIO_PULL_NONE);
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gpio_set_pull(GPIO_B33, GPIO_PULL_NONE);
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break;
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case PERIPH_ID_I2C2:
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gpio_cfg_pin(GPIO_A06, GPIO_FUNC(0x3));
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gpio_cfg_pin(GPIO_A07, GPIO_FUNC(0x3));
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gpio_set_pull(GPIO_A06, GPIO_PULL_NONE);
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gpio_set_pull(GPIO_A07, GPIO_PULL_NONE);
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break;
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case PERIPH_ID_I2C3:
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gpio_cfg_pin(GPIO_A12, GPIO_FUNC(0x3));
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gpio_cfg_pin(GPIO_A13, GPIO_FUNC(0x3));
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gpio_set_pull(GPIO_A12, GPIO_PULL_NONE);
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gpio_set_pull(GPIO_A13, GPIO_PULL_NONE);
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break;
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case PERIPH_ID_I2C4:
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gpio_cfg_pin(GPIO_A20, GPIO_FUNC(0x3));
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gpio_cfg_pin(GPIO_A21, GPIO_FUNC(0x3));
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gpio_set_pull(GPIO_A20, GPIO_PULL_NONE);
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gpio_set_pull(GPIO_A21, GPIO_PULL_NONE);
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break;
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case PERIPH_ID_I2C5:
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gpio_cfg_pin(GPIO_A22, GPIO_FUNC(0x3));
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gpio_cfg_pin(GPIO_A23, GPIO_FUNC(0x3));
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gpio_set_pull(GPIO_A22, GPIO_PULL_NONE);
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gpio_set_pull(GPIO_A23, GPIO_PULL_NONE);
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break;
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case PERIPH_ID_I2C6:
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gpio_cfg_pin(GPIO_B13, GPIO_FUNC(0x4));
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gpio_cfg_pin(GPIO_B14, GPIO_FUNC(0x4));
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break;
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case PERIPH_ID_I2C7:
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gpio_cfg_pin(GPIO_B22, GPIO_FUNC(0x3));
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gpio_cfg_pin(GPIO_B23, GPIO_FUNC(0x3));
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gpio_set_pull(GPIO_B22, GPIO_PULL_NONE);
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gpio_set_pull(GPIO_B23, GPIO_PULL_NONE);
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break;
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case PERIPH_ID_DPHPD:
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/* Set Hotplug detect for DP */
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gpio_cfg_pin(GPIO_X07, GPIO_FUNC(0x3));
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/*
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* Hotplug detect should have an external pullup; disable the
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* internal pulldown so they don't fight.
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*/
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gpio_set_pull(GPIO_X07, GPIO_PULL_NONE);
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break;
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case PERIPH_ID_I2S1:
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for (i = 0; i < 5; i++)
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gpio_cfg_pin(GPIO_B00 + i, GPIO_FUNC(0x02));
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break;
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default:
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printk(BIOS_DEBUG, "%s: invalid peripheral %d", __func__, peripheral);
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return -1;
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}
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return 0;
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}
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