dd2bc3f819
Old igd.asl had inconsistent addresses (between _DOD and actual device) and ghost devices. Any of those is enough to make brightness on windows fail and make igd.asl out-of-ACPI-spec. Also old code favoured ridiculous copying of the same thing 6 times per chipset. Leave only hooking up and chipset-specific part in chipset directory. Move NVS handling and ACPI-spec parts to a common file. Change-Id: I556769e5e28b83e7465e3db689e26c8c0ab44757 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7472 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
98 lines
2.4 KiB
C
98 lines
2.4 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc.
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*/
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#include <types.h>
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#include <string.h>
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#include <cbmem.h>
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#include <console/console.h>
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#include <arch/acpi.h>
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#include <arch/ioapic.h>
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#include <arch/acpigen.h>
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#include <arch/smp/mpspec.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <cpu/cpu.h>
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#include <cpu/x86/msr.h>
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#include <vendorcode/google/chromeos/gnvs.h>
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#include <ec/google/chromeec/ec.h>
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#include <southbridge/intel/lynxpoint/pch.h>
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#include <southbridge/intel/lynxpoint/nvs.h>
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#include "thermal.h"
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static void acpi_update_thermal_table(global_nvs_t *gnvs)
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{
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gnvs->tmps = CTL_TDP_SENSOR_ID;
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/* Normal TDP */
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gnvs->f1of = 0;
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gnvs->f1on = 0;
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/* Limited TDP */
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gnvs->f0of = CTL_TDP_THRESHOLD_OFF;
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gnvs->f0on = CTL_TDP_THRESHOLD_ON;
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gnvs->f0pw = CTL_TDP_POWER_LIMIT;
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gnvs->tcrt = CRITICAL_TEMPERATURE;
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gnvs->tpsv = PASSIVE_TEMPERATURE;
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gnvs->tmax = MAX_TEMPERATURE;
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gnvs->flvl = 1;
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}
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void acpi_create_gnvs(global_nvs_t *gnvs)
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{
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/* Enable USB ports in S3 */
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gnvs->s3u0 = 1;
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gnvs->s3u1 = 1;
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/* Disable USB ports in S5 */
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gnvs->s5u0 = 0;
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gnvs->s5u1 = 0;
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/* TPM Present */
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gnvs->tpmp = 1;
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#if CONFIG_CHROMEOS
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gnvs->chromeos.vbt2 = google_ec_running_ro() ?
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ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
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#endif
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acpi_update_thermal_table(gnvs);
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}
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unsigned long acpi_fill_madt(unsigned long current)
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{
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/* Local APICs */
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current = acpi_create_madt_lapics(current);
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/* IOAPIC */
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current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
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2, IO_APIC_ADDR, 0);
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/* INT_SRC_OVR */
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current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
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current, 0, 0, 2, 0);
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current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
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current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
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return current;
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}
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