dd2bc3f819
Old igd.asl had inconsistent addresses (between _DOD and actual device) and ghost devices. Any of those is enough to make brightness on windows fail and make igd.asl out-of-ACPI-spec. Also old code favoured ridiculous copying of the same thing 6 times per chipset. Leave only hooking up and chipset-specific part in chipset directory. Move NVS handling and ACPI-spec parts to a common file. Change-Id: I556769e5e28b83e7465e3db689e26c8c0ab44757 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7472 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
108 lines
2.7 KiB
C
108 lines
2.7 KiB
C
/*
|
|
* This file is part of the coreboot project.
|
|
*
|
|
* Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License as published by
|
|
* the Free Software Foundation; version 2 of the License.
|
|
*
|
|
* This program is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*
|
|
* You should have received a copy of the GNU General Public License
|
|
* along with this program; if not, write to the Free Software
|
|
* Foundation, Inc.
|
|
*/
|
|
|
|
#include <types.h>
|
|
#include <string.h>
|
|
#include <cbmem.h>
|
|
#include <console/console.h>
|
|
#include <arch/acpi.h>
|
|
#include <arch/ioapic.h>
|
|
#include <arch/acpigen.h>
|
|
#include <arch/smp/mpspec.h>
|
|
#include <device/device.h>
|
|
#include <device/pci.h>
|
|
#include <device/pci_ids.h>
|
|
#include <cpu/cpu.h>
|
|
#include <cpu/x86/msr.h>
|
|
#include <vendorcode/google/chromeos/gnvs.h>
|
|
|
|
#include <southbridge/intel/lynxpoint/pch.h>
|
|
#include <southbridge/intel/lynxpoint/nvs.h>
|
|
#include "thermal.h"
|
|
|
|
static void acpi_update_thermal_table(global_nvs_t *gnvs)
|
|
{
|
|
gnvs->f4of = FAN4_THRESHOLD_OFF;
|
|
gnvs->f4on = FAN4_THRESHOLD_ON;
|
|
gnvs->f4pw = FAN4_PWM;
|
|
|
|
gnvs->f3of = FAN3_THRESHOLD_OFF;
|
|
gnvs->f3on = FAN3_THRESHOLD_ON;
|
|
gnvs->f3pw = FAN3_PWM;
|
|
|
|
gnvs->f2of = FAN2_THRESHOLD_OFF;
|
|
gnvs->f2on = FAN2_THRESHOLD_ON;
|
|
gnvs->f2pw = FAN2_PWM;
|
|
|
|
gnvs->f1of = FAN1_THRESHOLD_OFF;
|
|
gnvs->f1on = FAN1_THRESHOLD_ON;
|
|
gnvs->f1pw = FAN1_PWM;
|
|
|
|
gnvs->f0of = FAN0_THRESHOLD_OFF;
|
|
gnvs->f0on = FAN0_THRESHOLD_ON;
|
|
gnvs->f0pw = FAN0_PWM;
|
|
|
|
gnvs->tcrt = CRITICAL_TEMPERATURE;
|
|
gnvs->tpsv = PASSIVE_TEMPERATURE;
|
|
gnvs->tmax = MAX_TEMPERATURE;
|
|
}
|
|
|
|
void acpi_create_gnvs(global_nvs_t *gnvs)
|
|
{
|
|
/* Enable USB ports in S3 */
|
|
gnvs->s3u0 = 1;
|
|
gnvs->s3u1 = 1;
|
|
|
|
/*
|
|
* Enable Front USB ports in S5 by default
|
|
* to be consistent with back port behavior
|
|
*/
|
|
gnvs->s5u0 = 1;
|
|
gnvs->s5u1 = 1;
|
|
|
|
/* TPM Present */
|
|
gnvs->tpmp = 1;
|
|
|
|
|
|
#if CONFIG_CHROMEOS
|
|
/* Emerald Lake has no EC (?) */
|
|
gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
|
|
#endif
|
|
|
|
acpi_update_thermal_table(gnvs);
|
|
}
|
|
|
|
unsigned long acpi_fill_madt(unsigned long current)
|
|
{
|
|
/* Local APICs */
|
|
current = acpi_create_madt_lapics(current);
|
|
|
|
/* IOAPIC */
|
|
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
|
|
2, IO_APIC_ADDR, 0);
|
|
|
|
/* INT_SRC_OVR */
|
|
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
|
|
current, 0, 0, 2, 0);
|
|
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
|
|
current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
|
|
|
|
return current;
|
|
}
|