dd2bc3f819
Old igd.asl had inconsistent addresses (between _DOD and actual device) and ghost devices. Any of those is enough to make brightness on windows fail and make igd.asl out-of-ACPI-spec. Also old code favoured ridiculous copying of the same thing 6 times per chipset. Leave only hooking up and chipset-specific part in chipset directory. Move NVS handling and ACPI-spec parts to a common file. Change-Id: I556769e5e28b83e7465e3db689e26c8c0ab44757 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7472 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
71 lines
2.2 KiB
Plaintext
71 lines
2.2 KiB
Plaintext
chip northbridge/intel/fsp_sandybridge
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# IGD Displays
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register "gfx.ndid" = "3"
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register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
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# Enable DisplayPort 1 Hotplug with 6ms pulse
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register "gpu_dp_d_hotplug" = "0x06"
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# Enable DisplayPort 0 Hotplug with 6ms pulse
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register "gpu_dp_c_hotplug" = "0x06"
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# Enable DVI Hotplug with 6ms pulse
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register "gpu_dp_b_hotplug" = "0x06"
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device cpu_cluster 0 on
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chip cpu/intel/socket_rPGA989
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device lapic 0 on end
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end
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chip cpu/intel/fsp_model_206ax
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# Magic APIC ID to locate this chip
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device lapic 0xACAC off end
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register "c1_battery" = "3" # ACPI(C1) = MWAIT(C3)
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register "c2_battery" = "4" # ACPI(C2) = MWAIT(C6)
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register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7)
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register "c1_acpower" = "3" # ACPI(C1) = MWAIT(C3)
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register "c2_acpower" = "4" # ACPI(C2) = MWAIT(C6)
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register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7)
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end
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end
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device domain 0 on
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device pci 00.0 on end # host bridge
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device pci 02.0 on end # vga controller
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chip southbridge/intel/fsp_bd82x6x # Intel Series 6 Cougar Point PCH
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register "sata_port_map" = "0x3f"
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register "c2_latency" = "1"
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register "p_cnt_throttling_supported" = "0"
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device pci 14.0 on end # XHCI
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device pci 16.0 on end # Management Engine Interface 1
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device pci 16.1 on end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT
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device pci 19.0 on end # Intel Gigabit Ethernet
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device pci 1a.0 on end # USB2 EHCI #2
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device pci 1b.0 off end # High Definition Audio
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device pci 1c.0 on end # PCIe Port #1
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device pci 1c.1 on end # PCIe Port #2
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device pci 1c.2 on end # PCIe Port #3
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device pci 1c.3 on end # PCIe Port #4
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device pci 1c.4 on end # PCIe Port #5
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device pci 1c.5 on end # PCIe Port #6
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device pci 1c.6 on end # PCIe Port #7
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device pci 1c.7 on end # PCIe Port #8
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device pci 1d.0 on end # USB2 EHCI #1
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device pci 1e.0 off end # PCI bridge
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device pci 1f.0 on # LPC bridge
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# TODO: insert SIO UART and WDT
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end
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device pci 1f.2 on end # SATA Controller 1
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device pci 1f.3 on end # SMBus
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device pci 1f.5 on end # SATA Controller 2
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device pci 1f.6 on end # Thermal
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end
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end
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end
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