deeccbf4e9
Unmentioned fields are initialized with 0 (or NULL) implicitly. Beside that, the struct has grown over the years. There are too many optional fields to list them all. Change-Id: Icb9e14c58153d7c14817bcde148e86e977666e4b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40126 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
54 lines
1.5 KiB
C
54 lines
1.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* This file is part of the coreboot project. */
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include "chip.h"
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#include "hudson.h"
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static void sd_init(struct device *dev)
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{
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struct southbridge_amd_pi_hudson_config *sd_chip = dev->chip_info;
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u32 stepping = pci_read_config32(pcidev_on_root(0x18, 3), 0xFC);
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u8 sd_mode = 0;
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if (sd_chip)
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sd_mode = sd_chip->sd_mode;
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if (sd_mode == 3) { /* SD 3.0 mode */
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pci_write_config32(dev, 0xA4, 0x31FEC8B2);
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pci_write_config32(dev, 0xA8, 0x00002503);
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pci_write_config32(dev, 0xB0, 0x02180C19);
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pci_write_config32(dev, 0xD0, 0x0000078B);
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}
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else { /* SD 2.0 mode */
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if ((stepping & 0x0000000F) == 0) { /* Stepping A0 */
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pci_write_config32(dev, 0xA4, 0x31DE32B2);
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pci_write_config32(dev, 0xB0, 0x01180C19);
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pci_write_config32(dev, 0xD0, 0x0000058B);
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}
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else { /* Stepping >= A1 */
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pci_write_config32(dev, 0xA4, 0x31FE32B2);
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pci_write_config32(dev, 0xA8, 0x00000070);
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pci_write_config32(dev, 0xB0, 0x01180C19);
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pci_write_config32(dev, 0xD0, 0x0000078B);
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}
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}
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}
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static struct device_operations sd_ops = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = sd_init,
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};
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static const struct pci_driver sd_driver __pci_driver = {
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.ops = &sd_ops,
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.vendor = PCI_VENDOR_ID_AMD,
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.device = PCI_DEVICE_ID_AMD_YANGTZE_SD,
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};
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