df0c822239
In preparation to support CBFS hosted microcode blobs, this change renames the wrapper include file containing the microcode to be independent of CPU model. Change-Id: If1a4963a52e5037a3a3495b90708ffc08b23f4c1 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/1294 Tested-by: build bot (Jenkins)
66 lines
1.7 KiB
C
66 lines
1.7 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <stdint.h>
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#include <arch/cpu.h>
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#include <cpu/x86/cache.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/mtrr.h>
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static const uint32_t microcode_updates[] = {
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#include "microcode_blob.h"
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};
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#include <cpu/intel/microcode/microcode.c>
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static void set_var_mtrr(
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unsigned reg, unsigned base, unsigned size, unsigned type)
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{
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/* Bit Bit 32-35 of MTRRphysMask should be set to 1 */
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/* FIXME: It only support 4G less range */
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msr_t basem, maskm;
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basem.lo = base | type;
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basem.hi = 0;
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wrmsr(MTRRphysBase_MSR(reg), basem);
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maskm.lo = ~(size - 1) | MTRRphysMaskValid;
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maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1;
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wrmsr(MTRRphysMask_MSR(reg), maskm);
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}
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static void enable_rom_caching(void)
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{
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msr_t msr;
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disable_cache();
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set_var_mtrr(1, 0xffc00000, 4*1024*1024, MTRR_TYPE_WRPROT);
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enable_cache();
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/* Enable Variable MTRRs */
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msr.hi = 0x00000000;
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msr.lo = 0x00000800;
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wrmsr(MTRRdefType_MSR, msr);
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}
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static void bootblock_cpu_init(void)
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{
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enable_rom_caching();
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intel_update_microcode(microcode_updates);
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}
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