dfeb1c4da9
Simplify funciton names and remove reference to hudson in stoneyridge. The southbridge in Stoney Ridge is Kern and hudson naming is no longer accurate. BUG=b:62200157 BRANCH=none TEST=Build and booted on Kahlee. Change-Id: Ide7a72dae69b881997101f1e37a1ac739901744d Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/20912 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
83 lines
2.3 KiB
C
83 lines
2.3 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2010 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <console/console.h>
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#include <device/device.h>
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#include <delay.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include <arch/io.h>
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#include <soc/southbridge.h>
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static void sata_init(struct device *dev)
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{
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/**************************************
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* Configure the SATA port multiplier *
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**************************************/
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#define BYTE_TO_DWORD_OFFSET(x) (x/4)
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#define AHCI_BASE_ADDRESS_REG 0x24
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#define MISC_CONTROL_REG 0x40
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#define UNLOCK_BIT (1<<0)
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#define SATA_CAPABILITIES_REG 0xfc
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#define CFG_CAP_SPM (1<<12)
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volatile u32 *ahci_ptr = (u32 *)(pci_read_config32(dev,
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AHCI_BASE_ADDRESS_REG) & 0xffffff00);
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u32 temp;
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/* unlock the write-protect */
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temp = pci_read_config32(dev, MISC_CONTROL_REG);
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temp |= UNLOCK_BIT;
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pci_write_config32(dev, MISC_CONTROL_REG, temp);
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/* set the SATA AHCI mode to allow port expanders */
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*(ahci_ptr + BYTE_TO_DWORD_OFFSET(SATA_CAPABILITIES_REG))
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|= CFG_CAP_SPM;
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/* lock the write-protect */
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temp = pci_read_config32(dev, MISC_CONTROL_REG);
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temp &= ~UNLOCK_BIT;
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pci_write_config32(dev, MISC_CONTROL_REG, temp);
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};
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static struct pci_operations lops_pci = {
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/* .set_subsystem = pci_dev_set_subsystem, */
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};
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static struct device_operations sata_ops = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = sata_init,
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.scan_bus = 0,
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.ops_pci = &lops_pci,
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};
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static const unsigned short pci_device_ids[] = {
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PCI_DEVICE_ID_AMD_SB900_SATA,
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PCI_DEVICE_ID_AMD_SB900_SATA_AHCI,
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PCI_DEVICE_ID_AMD_CZ_SATA,
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PCI_DEVICE_ID_AMD_CZ_SATA_AHCI,
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0
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};
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static const struct pci_driver sata0_driver __pci_driver = {
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.ops = &sata_ops,
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.vendor = PCI_VENDOR_ID_AMD,
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.devices = pci_device_ids,
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};
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