dff185a28d
The result is that i82801{g,i,j}x now use the correct _PRT table for
their root port number.
Change-Id: I92bba3c669f3e6a44a42e19a88a33dfcfc2b9b42
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
203 lines
4.0 KiB
Plaintext
203 lines
4.0 KiB
Plaintext
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* Intel 82801Ix support */
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Scope(\)
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{
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// IO-Trap at 0x800. This is the ACPI->SMI communication interface.
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OperationRegion(IO_T, SystemIO, 0x800, 0x10)
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Field(IO_T, ByteAcc, NoLock, Preserve)
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{
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Offset(0x8),
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TRP0, 8 // IO-Trap at 0x808
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}
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// ICH10 Power Management Registers, located at PMBASE (0x1f.0 0x40.l)
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OperationRegion(PMIO, SystemIO, DEFAULT_PMBASE, 0x80)
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Field(PMIO, ByteAcc, NoLock, Preserve)
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{
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Offset(0x11),
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THRO, 1, // force thermal throttling
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Offset(0x42), // General Purpose Control
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, 1, // skip 1 bit
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GPEC, 1, // TCO status
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Offset(0x64),
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, 9, // skip 9 more bits
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SCIS, 1 // TCO DMI status
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}
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// ICH10 GPIO IO mapped registers (0x1f.0 reg 0x48.l)
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OperationRegion(GPIO, SystemIO, DEFAULT_GPIOBASE, 0x3c)
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Field(GPIO, ByteAcc, NoLock, Preserve)
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{
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Offset(0x00), // GPIO Use Select
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GU00, 8,
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GU01, 8,
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GU02, 8,
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GU03, 8,
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Offset(0x04), // GPIO IO Select
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GIO0, 8,
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GIO1, 8,
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GIO2, 8,
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GIO3, 8,
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Offset(0x0c), // GPIO Level
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GP00, 1,
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GP01, 1,
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GP02, 1,
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GP03, 1,
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GP04, 1,
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GP05, 1,
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GP06, 1,
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GP07, 1,
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GP08, 1,
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GP09, 1,
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GP10, 1,
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GP11, 1,
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GP12, 1,
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GP13, 1,
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GP14, 1,
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GP15, 1,
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GP16, 1,
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GP17, 1,
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GP18, 1,
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GP19, 1,
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GP20, 1,
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GP21, 1,
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GP22, 1,
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GP23, 1,
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GP24, 1,
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GP25, 1,
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GP26, 1,
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GP27, 1,
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GP28, 1,
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GP29, 1,
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GP30, 1,
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GP31, 1,
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Offset(0x18), // GPIO Blink
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GB00, 8,
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GB01, 8,
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GB02, 8,
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GB03, 8,
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Offset(0x2c), // GPIO Invert
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GIV0, 8,
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GIV1, 8,
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GIV2, 8,
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GIV3, 8,
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Offset(0x30), // GPIO Use Select 2
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GU04, 8,
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GU05, 8,
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GU06, 8,
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GU07, 8,
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Offset(0x34), // GPIO IO Select 2
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GIO4, 8,
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GIO5, 8,
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GIO6, 8,
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GIO7, 8,
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Offset(0x38), // GPIO Level 2
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GP32, 1,
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GP33, 1,
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GP34, 1,
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GP35, 1,
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GP36, 1,
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GP37, 1,
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GP38, 1,
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GP39, 1,
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GL05, 8,
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GL06, 8,
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GL07, 8
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}
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// ICH10 Root Complex Register Block. Memory Mapped through RCBA)
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OperationRegion(RCRB, SystemMemory, DEFAULT_RCBA, 0x4000)
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Field(RCRB, DWordAcc, Lock, Preserve)
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{
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Offset(0x0000), // Backbone
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Offset(0x1000), // Chipset
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Offset(0x3000), // Legacy Configuration Registers
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Offset(0x3404), // High Performance Timer Configuration
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HPAS, 2, // Address Select
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, 5,
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HPTE, 1, // Address Enable
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Offset(0x3418), // FD (Function Disable)
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, 2, // Reserved
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SA1D, 1, // SATA disable
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SMBD, 1, // SMBUS disable
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HDAD, 1, // Azalia disable
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, 2, // Reserved
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US6D, 1, // UHCI #6 disable
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US1D, 1, // UHCI #1 disable
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US2D, 1, // UHCI #2 disable
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US3D, 1, // UHCI #3 disable
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US4D, 1, // UHCI #4 disable
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US5D, 1, // UHCI #5 disable
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EH2D, 1, // EHCI disable
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LPBD, 1, // LPC bridge disable
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EH1D, 1, // EHCI disable
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Offset(0x341a), // FD Root Ports
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RP1D, 1, // Root Port 1 disable
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RP2D, 1, // Root Port 2 disable
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RP3D, 1, // Root Port 3 disable
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RP4D, 1, // Root Port 4 disable
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RP5D, 1, // Root Port 5 disable
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RP6D, 1, // Root Port 6 disable
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, 2, // Reserved
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THRD, 1, // Thermal Throttle disable
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SA2D, 1, // SATA disable
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}
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}
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// 0:1b.0 High Definition Audio (Azalia)
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#include "audio.asl"
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// PCI Express Ports
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#include <southbridge/intel/common/acpi/pcie.asl>
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// USB
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#include "usb.asl"
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// PCI Bridge
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#include "pci.asl"
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// LPC Bridge
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#include "lpc.asl"
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// SATA
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#include "sata.asl"
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// SMBus
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#include "smbus.asl"
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Method (_OSC, 4)
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{
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/* Check for proper GUID */
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If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")))
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{
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/* Let OS control everything */
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Return (Arg3)
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}
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Else
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{
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/* Unrecognized UUID */
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CreateDWordField (Arg3, 0, CDW1)
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Or (CDW1, 4, CDW1)
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Return (Arg3)
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}
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}
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