dffb1c8933
This patch removes the wbinvd call preceding CR0.CD setting in
disable_cache() to improve the boot time performances. According to
some experimental measurements, the wbinvd execution takes between 1.6
up and 6 milliseconds to complete so it is preferable to call it only
when necessary.
According to Intel Software Developer Manual Vol 3.A - 12.5.3
Preventing Caching section there is no need to flush and invalidate
the cache before settings CR0.CD. The documented sequence consists in
setting CR0.CD and then call wbinvd.
We also could not find any extra requirements in the AMD64
Architecture Programmer’s Manual - Volume 2 - Memory System chapter.
This extra wbinvd in coreboot disable_cache() function does not seem
documented and looking into the history of the project got us all the
way back to original commit 8ca8d7665d67 ("- Initial checkin of the
freebios2 tree") from April 2003.
Even the original disable_cache() implementation (see below) is a bit
curious as the comment list two actions:
1. Disable cache cover by line 74, 75 and 77
2. Write back the cache and flush TLB - Line 78
But it does not provide any explanation for the wbinvd call line 76.
68 static inline void disable_cache(void)
69 {
70 unsigned int tmp;
71 /* Disable cache */
72 /* Write back the cache and flush TLB */
73 asm volatile (
74 "movl %%cr0, %0\n\t"
75 "orl $0x40000000, %0\n\t"
76 "wbinvd\n\t"
77 "movl %0, %%cr0\n\t"
78 "wbinvd\n\t"
79 :"=r" (tmp)
80 ::"memory");
81 }
BUG=b/260455826
TEST=Successful boot on Skolas and Rex board
Change-Id: I08c6486dc93c4d70cadc22a760d1b7e536e85bfa
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com>
66 lines
1.5 KiB
C
66 lines
1.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef CPU_X86_CACHE
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#define CPU_X86_CACHE
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#include <cpu/x86/cr.h>
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#define CR0_CacheDisable (CR0_CD)
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#define CR0_NoWriteThrough (CR0_NW)
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#define CPUID_FEATURE_CLFLUSH_BIT 19
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#if !defined(__ASSEMBLER__)
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#include <stdbool.h>
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#include <stddef.h>
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static inline void wbinvd(void)
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{
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asm volatile ("wbinvd" ::: "memory");
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}
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static inline void invd(void)
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{
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asm volatile("invd" ::: "memory");
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}
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static inline void clflush(void *addr)
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{
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asm volatile ("clflush (%0)"::"r" (addr));
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}
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bool clflush_supported(void);
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void clflush_region(const uintptr_t start, const size_t size);
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/* The following functions require the __always_inline due to AMD
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* function STOP_CAR_AND_CPU that disables cache as
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* RAM, the cache as RAM stack can no longer be used. Called
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* functions must be inlined to avoid stack usage. Also, the
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* compiler must keep local variables register based and not
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* allocated them from the stack. With gcc 4.5.0, some functions
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* declared as inline are not being inlined. This patch forces
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* these functions to always be inlined by adding the qualifier
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* __always_inline to their declaration.
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*/
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static __always_inline void enable_cache(void)
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{
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CRx_TYPE cr0;
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cr0 = read_cr0();
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cr0 &= ~(CR0_CD | CR0_NW);
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write_cr0(cr0);
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}
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static __always_inline void disable_cache(void)
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{
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/* Disable and write back the cache */
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CRx_TYPE cr0;
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cr0 = read_cr0();
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cr0 |= CR0_CD;
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write_cr0(cr0);
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wbinvd();
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}
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#endif /* !__ASSEMBLER__ */
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#endif /* CPU_X86_CACHE */
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