46f04cbb49
Drop all the sources that were guarded with this. Change-Id: I6c6fd19875cb57f0caf42a1a94f59efed83bfe0d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/19275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
209 lines
7.7 KiB
C
209 lines
7.7 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <AGESA.h>
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#include <PlatformMemoryConfiguration.h>
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static const PCIe_PORT_DESCRIPTOR PortList[] = {
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/* Initialize Port descriptor (PCIe port, Lane 3, PCI Device 2, Function 5) */
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 3, 3),
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PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 5,
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HotplugDisabled,
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PcieGenMaxSupported,
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PcieGenMaxSupported,
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AspmDisabled, 0x01, 0)
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},
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/* Initialize Port descriptor (PCIe port, Lane 2, PCI Device 2, Function 4) */
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 2, 2),
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PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 4,
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HotplugDisabled,
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PcieGenMaxSupported,
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PcieGenMaxSupported,
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AspmDisabled, 0x02, 0)
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},
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/* Initialize Port descriptor (PCIe port, Lane 1, PCI Device 2, Function 3) */
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 1, 1),
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PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 3,
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HotplugDisabled,
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PcieGenMaxSupported,
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PcieGenMaxSupported,
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AspmDisabled, 0x03, 0)
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},
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/* Initialize Port descriptor (PCIe port, Lane 0, PCI Device 2, Function 2) */
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 0),
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PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 2,
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HotplugDisabled,
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PcieGenMaxSupported,
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PcieGenMaxSupported,
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AspmDisabled, 0x04, 0)
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},
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/* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device 2, Function 1) */
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{
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DESCRIPTOR_TERMINATE_LIST,
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PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7),
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PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 1,
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HotplugDisabled,
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PcieGenMaxSupported,
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PcieGenMaxSupported,
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AspmDisabled, 0x05, 0)
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}
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};
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static const PCIe_DDI_DESCRIPTOR DdiList[] = {
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/* DP0 to HDMI0/DP */
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{
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DESCRIPTOR_TERMINATE_LIST,
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PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
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PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux1, Hdp1)
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},
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};
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static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
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.Flags = DESCRIPTOR_TERMINATE_LIST,
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.SocketId = 0,
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.PciePortList = PortList,
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.DdiLinkList = DdiList
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};
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/*---------------------------------------------------------------------------------------*/
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/**
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* OemCustomizeInitEarly
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*
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* Description:
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* This stub function will call the host environment through the binary block
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* interface (call-out port) to provide a user hook opportunity
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*
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* Parameters:
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* @param[in] *InitEarly
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*
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* @retval VOID
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*
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**/
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/*---------------------------------------------------------------------------------------*/
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VOID
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OemCustomizeInitEarly (
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IN OUT AMD_EARLY_PARAMS *InitEarly
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)
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{
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InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
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}
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/*
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* Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
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* (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
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* is populated, AGESA will base its settings on the data from the table. Otherwise, it will
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* use its default conservative settings.
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*/
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static const PSO_ENTRY ROMDATA PlatformMemoryConfiguration[] = {
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/*
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* The following macros are supported (use comma to separate macros):
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*
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* MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap)
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* The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap.
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* AGESA will base on this value to disable unused MemClk to save power.
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* Example:
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* BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below:
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* Bit AM3/S1g3 pin name
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* 0 M[B,A]_CLK_H/L[0]
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* 1 M[B,A]_CLK_H/L[1]
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* 2 M[B,A]_CLK_H/L[2]
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* 3 M[B,A]_CLK_H/L[3]
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* 4 M[B,A]_CLK_H/L[4]
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* 5 M[B,A]_CLK_H/L[5]
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* 6 M[B,A]_CLK_H/L[6]
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* 7 M[B,A]_CLK_H/L[7]
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* And platform has the following routing:
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* CS0 M[B,A]_CLK_H/L[4]
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* CS1 M[B,A]_CLK_H/L[2]
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* CS2 M[B,A]_CLK_H/L[3]
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* CS3 M[B,A]_CLK_H/L[5]
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* Then platform can specify the following macro:
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* MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00)
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*
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* CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap)
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* The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap.
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* AGESA will base on this value to tristate unused CKE to save power.
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*
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* ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap)
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* The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap.
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* AGESA will base on this value to tristate unused ODT pins to save power.
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*
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* CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap)
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* The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap.
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* AGESA will base on this value to tristate unused Chip select to save power.
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*
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* NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel)
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* Specifies the number of DIMM slots per channel.
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*
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* NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel)
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* Specifies the number of Chip selects per channel.
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*
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* NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket)
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* Specifies the number of channels per socket.
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*
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* OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED)
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* Specifies DDR bus speed of channel ChannelID on socket SocketID.
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*
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* DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE)
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* Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...)
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*
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* WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
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* Byte6Seed, Byte7Seed, ByteEccSeed)
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* Specifies the write leveling seed for a channel of a socket.
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*
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* HW_RXEN_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
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* Byte6Seed, Byte7Seed, ByteEccSeed)
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* Speicifes the HW RXEN training seed for a channel of a socket
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*/
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#define SEED_WL 0x0E
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WRITE_LEVELING_SEED(
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ANY_SOCKET, CHANNEL_A, ALL_DIMMS,
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SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL,
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SEED_WL),
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#define SEED_A 0x12
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HW_RXEN_SEED(
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ANY_SOCKET, CHANNEL_A, ALL_DIMMS,
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SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A,
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SEED_A),
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NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 1),
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NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1),
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MOTHER_BOARD_LAYERS(LAYERS_6),
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MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
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CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), /* TODO: bit2map, bit3map */
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ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08),
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CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00),
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PSO_END
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};
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void OemPostParams(AMD_POST_PARAMS *PostParams)
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{
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/* Add the memory configuration table needed for soldered down memory */
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PostParams->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryConfiguration;
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}
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