e18cdf4d93
Some settings are suspicious, and have been annotated with FIXMEs. Tested with BUILD_TIMELESS=1, its coreboot.rom does not change. Change-Id: I7755867cb92745f542a4261db5dd118ca905612b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43919 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
398 lines
13 KiB
Plaintext
398 lines
13 KiB
Plaintext
## SPDX-License-Identifier: GPL-2.0-only
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chip soc/intel/skylake
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register "deep_s3_enable_ac" = "0"
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register "deep_s3_enable_dc" = "0"
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register "deep_s5_enable_ac" = "0"
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register "deep_s5_enable_dc" = "0"
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register "deep_sx_config" = "DSX_EN_WAKE_PIN"
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register "eist_enable" = "1"
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# GPE configuration
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# Note that GPE events called out in ASL code rely on this
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# route. i.e. If this route changes then the affected GPE
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# offset bits also need to be changed.
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register "gpe0_dw0" = "GPP_B"
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register "gpe0_dw1" = "GPP_D"
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register "gpe0_dw2" = "GPP_E"
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# Enable "Intel Speed Shift Technology"
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register "speed_shift_enable" = "1"
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# Enable DPTF
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register "dptf_enable" = "1"
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# FSP Configuration
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register "PrimaryDisplay" = "Display_PEG"
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register "SaGv" = "SaGv_Enabled"
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register "PmTimerDisabled" = "0"
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# Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
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# SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s
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register "PmConfigSlpS3MinAssert" = "0x02"
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# SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s
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register "PmConfigSlpS4MinAssert" = "0x04"
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# SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s
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register "PmConfigSlpSusMinAssert" = "0x03"
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# SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s
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register "PmConfigSlpAMinAssert" = "0x03"
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# VR Settings Configuration
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#+----------------+-------+-------+-------------+-------+
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#| Domain/Setting | SA | IA | GT Unsliced | GT |
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#+----------------+-------+-------+-------------+-------+
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#| Psi1Threshold | 20A | 20A | 20A | 20A |
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#| Psi2Threshold | 4A | 5A | 5A | 5A |
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#| Psi3Threshold | 1A | 1A | 1A | 1A |
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#| Psi3Enable | 1 | 1 | 1 | 1 |
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#| Psi4Enable | 1 | 1 | 1 | 1 |
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#| ImonSlope | 0 | 0 | 0 | 0 |
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#| ImonOffset | 0 | 0 | 0 | 0 |
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#| IccMax* | 0 | 0 | 0 | 0 |
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#| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
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#+----------------+-------+-------+-------------+-------+
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# * - is set automatically in the vr_config.c
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register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
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.vr_config_enable = 1, \
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.psi1threshold = VR_CFG_AMP(20), \
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.psi2threshold = VR_CFG_AMP(4), \
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.psi3threshold = VR_CFG_AMP(1), \
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.psi3enable = 1, \
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.psi4enable = 1, \
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.imon_slope = 0x0, \
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.imon_offset = 0x0, \
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.icc_max = 0x0, \
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.voltage_limit = 1520 \
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}"
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register "domain_vr_config[VR_IA_CORE]" = "{
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.vr_config_enable = 1, \
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.psi1threshold = VR_CFG_AMP(20), \
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.psi2threshold = VR_CFG_AMP(5), \
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.psi3threshold = VR_CFG_AMP(1), \
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.psi3enable = 1, \
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.psi4enable = 1, \
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.imon_slope = 0x0, \
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.imon_offset = 0x0, \
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.icc_max = 0x0, \
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.voltage_limit = 1520 \
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}"
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register "domain_vr_config[VR_GT_UNSLICED]" = "{
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.vr_config_enable = 1, \
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.psi1threshold = VR_CFG_AMP(20), \
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.psi2threshold = VR_CFG_AMP(5), \
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.psi3threshold = VR_CFG_AMP(1), \
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.psi3enable = 1, \
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.psi4enable = 1, \
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.imon_slope = 0x0, \
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.imon_offset = 0x0, \
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.icc_max = 0x0 ,\
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.voltage_limit = 1520 \
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}"
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register "domain_vr_config[VR_GT_SLICED]" = "{
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.vr_config_enable = 1, \
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.psi1threshold = VR_CFG_AMP(20), \
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.psi2threshold = VR_CFG_AMP(5), \
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.psi3threshold = VR_CFG_AMP(1), \
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.psi3enable = 1, \
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.psi4enable = 1, \
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.imon_slope = 0x0, \
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.imon_offset = 0x0, \
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.icc_max = 0x0, \
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.voltage_limit = 1520 \
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}"
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# PCH UART, SPI, I2C
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register "SerialIoDevMode" = "{ \
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[PchSerialIoIndexI2C0] = PchSerialIoDisabled, \
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[PchSerialIoIndexI2C1] = PchSerialIoDisabled, \
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[PchSerialIoIndexI2C2] = PchSerialIoDisabled, \
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[PchSerialIoIndexI2C3] = PchSerialIoDisabled, \
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[PchSerialIoIndexI2C4] = PchSerialIoDisabled, \
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[PchSerialIoIndexI2C5] = PchSerialIoDisabled, \
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[PchSerialIoIndexSpi0] = PchSerialIoDisabled, \
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[PchSerialIoIndexSpi1] = PchSerialIoDisabled, \
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[PchSerialIoIndexUart0] = PchSerialIoDisabled, \
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[PchSerialIoIndexUart1] = PchSerialIoDisabled, \
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[PchSerialIoIndexUart2] = PchSerialIoDisabled, \
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}"
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# PL2 override 91W
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register "power_limits_config" = "{
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.tdp_pl2_override = 91,
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}"
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# Send an extra VR mailbox command for the PS4 exit issue
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register "SendVrMbxCmd" = "2"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device domain 0 on
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device pci 00.0 on # Host Bridge
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subsystemid 0x1849 0x191f
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end
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device pci 01.0 on # PEG
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subsystemid 0x1849 0x1901
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register "Peg0MaxLinkWidth" = "Peg0_x16"
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register "SkipExtGfxScan" = "0"
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# Configure PCIe clockgen in PCH
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register "PcieRpClkReqSupport[0]" = "1"
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register "PcieRpClkReqNumber[0]" = "0"
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register "PcieRpClkSrcNumber[0]" = "0"
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end
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device pci 02.0 on # Integrated Graphics Device
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subsystemid 0x1849 0x1912
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end
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device pci 04.0 on # Thermal Subsystem
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register "Device4Enable" = "1"
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end
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device pci 08.0 off end # Gaussian Mixture Model
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device pci 14.0 on # USB xHCI
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subsystemid 0x1849 0xa131
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register "usb2_ports[0]" = "USB2_PORT_MID(OC0)"
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register "usb2_ports[1]" = "USB2_PORT_MID(OC0)"
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register "usb2_ports[2]" = "USB2_PORT_MID(OC4)"
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register "usb2_ports[3]" = "USB2_PORT_MID(OC4)"
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register "usb2_ports[4]" = "USB2_PORT_MID(OC2)"
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register "usb2_ports[5]" = "USB2_PORT_MID(OC2)"
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register "usb2_ports[6]" = "USB2_PORT_MID(OC0)"
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register "usb2_ports[7]" = "USB2_PORT_MID(OC0)"
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register "usb2_ports[8]" = "USB2_PORT_MID(OC0)"
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register "usb2_ports[9]" = "USB2_PORT_MID(OC0)"
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register "usb2_ports[10]" = "USB2_PORT_MID(OC1)"
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register "usb2_ports[11]" = "USB2_PORT_MID(OC1)"
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register "usb2_ports[12]" = "USB2_PORT_MID(OC_SKIP)"
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register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)"
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register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"
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register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"
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register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)"
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register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)"
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register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)"
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register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)"
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register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC_SKIP)"
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register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC_SKIP)"
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register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC_SKIP)"
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register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC_SKIP)"
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end
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device pci 14.1 off end # USB xDCI (OTG)
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device pci 14.2 on # Thermal Subsystem
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subsystemid 0x1849 0xa131
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end
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device pci 15.0 off end # I2C #0
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device pci 15.1 off end # I2C #1
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device pci 15.2 off end # I2C #2
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device pci 15.3 off end # I2C #3
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device pci 16.0 on # Management Engine Interface 1
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subsystemid 0x1849 0xa131
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# FIXME: does not match devicetree!
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register "HeciEnabled" = "0"
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end
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT Redirection
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device pci 16.4 off end # Management Engine Interface 3
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device pci 17.0 on # SATA
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subsystemid 0x1849 0xa102
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register "SataSalpSupport" = "1"
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# SATA4 and SATA5 are located in the lower right corner of the board,
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# but they are not populated. This is because the same PCB is used to
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# make boards with better PCHs, which can have up to six SATA ports.
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# However, the H110 PCH only has four SATA ports, which explains why
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# two connectors are missing.
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register "SataPortsEnable" = "{ \
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[0] = 1, \
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[1] = 1, \
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[2] = 1, \
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[3] = 1, \
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[4] = 0, \
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[5] = 0, \
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[6] = 0, \
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[7] = 0, \
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}"
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end
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device pci 19.0 off end # UART #2
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device pci 19.1 off end # I2C #5
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device pci 19.2 off end # I2C #4
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device pci 1c.0 on end # PCI Express Port 1
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device pci 1c.1 off end # PCI Express Port 2
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device pci 1c.2 off end # PCI Express Port 3
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device pci 1c.3 off end # PCI Express Port 4
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device pci 1c.4 on # PCI Express Port 5 - PCIE slot
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register "PcieRpEnable[4]" = "1"
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register "PcieRpClkReqSupport[4]" = "1"
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register "PcieRpClkReqNumber[4]" = "2"
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register "PcieRpAdvancedErrorReporting[4]" = "1"
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register "PcieRpLtrEnable[4]" = "1"
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register "PcieRpClkSrcNumber[4]" = "2"
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register "PcieRpHotPlug[4]" = "1"
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end
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device pci 1c.5 on # PCI Express Port 6 - Onboard LAN
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register "PcieRpEnable[5]" = "1"
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# Disable CLKREQ#, since onboard LAN is always present
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register "PcieRpClkReqSupport[5]" = "0"
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register "PcieRpAdvancedErrorReporting[5]" = "1"
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register "PcieRpLtrEnable[5]" = "1"
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register "PcieRpClkSrcNumber[5]" = "1"
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end
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device pci 1c.6 on # PCI Express Port 7 - PCIE slot
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register "PcieRpEnable[6]" = "1"
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register "PcieRpClkReqSupport[6]" = "1"
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register "PcieRpClkReqNumber[6]" = "3"
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register "PcieRpAdvancedErrorReporting[6]" = "1"
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register "PcieRpLtrEnable[6]" = "1"
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register "PcieRpClkSrcNumber[6]" = "3"
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register "PcieRpHotPlug[6]" = "1"
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end
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device pci 1c.7 off end # PCI Express Port 8
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device pci 1d.0 off end # PCI Express Port 9
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device pci 1d.1 off end # PCI Express Port 10
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device pci 1d.2 off end # PCI Express Port 11
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device pci 1d.3 off end # PCI Express Port 12
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device pci 1e.0 off end # UART #0
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device pci 1e.1 off end # UART #1
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device pci 1e.2 off end # GSPI #0
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device pci 1e.3 off end # GSPI #1
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device pci 1e.4 off end # eMMC
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device pci 1e.5 off end # SDIO
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device pci 1e.6 off # SDCard
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register "ScsSdCardEnabled" = "0"
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end
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device pci 1f.0 on # LPC bridge
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subsystemid 0x1849 0x1a43
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# Set @0x280-0x2ff I/O Range for SuperIO HWM
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register "gen1_dec" = "0x007c0281"
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# Set LPC Serial IRQ mode
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register "serirq_mode" = "SERIRQ_CONTINUOUS"
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chip superio/common
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device pnp 2e.0 on # passes SIO base addr to SSDT gen
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chip superio/nuvoton/nct6791d
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device pnp 2e.1 on
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# Global Control Registers
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# Device IRQ Polarity
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irq 0x13 = 0x00
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irq 0x14 = 0x00
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# Global Option
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irq 0x24 = 0xfb
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irq 0x27 = 0x10
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# Multi Function
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irq 0x1a = 0xb0
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irq 0x1b = 0xe6
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irq 0x2a = 0x04
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irq 0x2c = 0x40
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irq 0x2d = 0x03
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# Parallel Port
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io 0x60 = 0x0378
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irq 0x70 = 7
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drq 0x74 = 4 # No DMA
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irq 0xf0 = 0x3c # Printer mode
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end
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device pnp 2e.2 on # UART A
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io 0x60 = 0x03f8
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irq 0x70 = 4
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end
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device pnp 2e.3 on # IR
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io 0x60 = 0x02f8
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irq 0x70 = 3
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end
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device pnp 2e.5 on # PS/2 KBC
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io 0x60 = 0x0060
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io 0x62 = 0x0064
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irq 0x70 = 1 # Keyboard
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irq 0x72 = 12 # Mouse
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end
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device pnp 2e.6 off end # CIR
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device pnp 2e.7 on # GPIO6
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irq 0xf6 = 0xff
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irq 0xf7 = 0xff
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irq 0xf8 = 0xff
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end
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device pnp 2e.107 on # GPIO7
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irq 0xe0 = 0x7f
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irq 0xe1 = 0x0d
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end
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device pnp 2e.207 on # GPIO8
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irq 0xe6 = 0xff
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irq 0xe7 = 0xff
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irq 0xed = 0xff
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end
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device pnp 2e.8 off end # WDT
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device pnp 2e.108 on end # GPIO0
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device pnp 2e.308 off end # GPIO base
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device pnp 2e.408 off end # WDTMEM
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device pnp 2e.708 on end # GPIO1
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device pnp 2e.9 on end # GPIO2
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device pnp 2e.109 on # GPIO3
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irq 0xe4 = 0x7b
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irq 0xe5 = 0x02
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irq 0xea = 0x04
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end
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device pnp 2e.209 on # GPIO4
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irq 0xf0 = 0x7f
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irq 0xf1 = 0x80
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end
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device pnp 2e.309 on # GPIO5
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irq 0xf4 = 0xdf
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irq 0xf5 = 0xd5
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end
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device pnp 2e.a on
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# Power RAM in S3 and let the PCH
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# handle power failure actions
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irq 0xe4 = 0x70
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# Set HWM reset source to LRESET#
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irq 0xe7 = 0x01
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end # ACPI
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device pnp 2e.b on # HWM, LED
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io 0x60 = 0x0290
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io 0x62 = 0
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irq 0x70 = 0
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end
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device pnp 2e.d off end # BCLK, WDT2, WDT_MEM
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device pnp 2e.e off end # CIR wake-up
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device pnp 2e.f off end # GPIO PP/OD
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device pnp 2e.14 off end # SVID, Port 80 UART
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device pnp 2e.16 off end # DS5
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device pnp 2e.116 off end # DS3
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device pnp 2e.316 on end # PCHDSW
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device pnp 2e.416 off end # DSWWOPT
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device pnp 2e.516 on end # DS3OPT
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device pnp 2e.616 on end # DSDSS
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device pnp 2e.716 off end # DSPU
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end # chip superio/nuvoton/nct6791d
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end # device pnp 2e.0
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end # chip superio/common
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chip drivers/pc80/tpm
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device pnp 4e.0 on end # TPM module
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end
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end # LPC Interface
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device pci 1f.1 on end # P2SB
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device pci 1f.2 on end # Power Management Controller
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device pci 1f.3 on # Intel HDA
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register "PchHdaVcType" = "Vc1"
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register "DspEnable" = "0"
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end
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device pci 1f.4 on end # SMBus
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device pci 1f.5 on end # PCH SPI
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device pci 1f.6 off end # GbE
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end
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end
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