e1a616cf99
Also drop now-redundant definitions and include headers where needed. Tested with BUILD_TIMELESS=1, Roda RK9 remains identical. Change-Id: I3ddd133a4e81a7f6ce9c33ce227b40006a0d1850 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42658 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
87 lines
2.6 KiB
C
87 lines
2.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <arch/io.h>
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#include <device/pci_ops.h>
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#include <device/smbus_host.h>
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#include <southbridge/intel/common/pmutil.h>
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#include "i82801ix.h"
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#include "chip.h"
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void i82801ix_lpc_setup(void)
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{
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const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0);
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const struct device *dev = pcidev_on_root(0x1f, 0);
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const struct southbridge_intel_i82801ix_config *config = NULL;
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/* Configure serial IRQs.*/
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pci_write_config8(d31f0, D31F0_SERIRQ_CNTL, 0xd0);
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/*
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* Enable some common LPC IO ranges:
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* - 0x2e/0x2f, 0x4e/0x4f often SuperIO
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* - 0x60/0x64, 0x62/0x66 often KBC/EC
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* - 0x3f0-0x3f5/0x3f7 FDD
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* - 0x378-0x37f and 0x778-0x77f LPT
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* - 0x2f8-0x2ff COMB
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* - 0x3f8-0x3ff COMA
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* - 0x208-0x20f GAMEH
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* - 0x200-0x207 GAMEL
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*/
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pci_write_config16(d31f0, D31F0_LPC_IODEC, 0x0010);
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pci_write_config16(d31f0, D31F0_LPC_EN, 0x3f0f);
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/* Set up generic decode ranges */
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if (!dev || !dev->chip_info)
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return;
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config = dev->chip_info;
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pci_write_config32(d31f0, D31F0_GEN1_DEC, config->gen1_dec);
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pci_write_config32(d31f0, D31F0_GEN2_DEC, config->gen2_dec);
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pci_write_config32(d31f0, D31F0_GEN3_DEC, config->gen3_dec);
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pci_write_config32(d31f0, D31F0_GEN4_DEC, config->gen4_dec);
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}
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void i82801ix_early_init(void)
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{
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const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0);
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if (ENV_ROMSTAGE)
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enable_smbus();
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/* Set up RCBA. */
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pci_write_config32(d31f0, RCBA, (uintptr_t)DEFAULT_RCBA | 1);
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/* Set up PMBASE. */
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pci_write_config32(d31f0, D31F0_PMBASE, DEFAULT_PMBASE | 1);
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/* Enable PMBASE. */
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pci_write_config8(d31f0, D31F0_ACPI_CNTL, 0x80);
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/* Set up GPIOBASE. */
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pci_write_config32(d31f0, D31F0_GPIO_BASE, DEFAULT_GPIOBASE);
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/* Enable GPIO. */
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pci_or_config8(d31f0, D31F0_GPIO_CNTL, 0x10);
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/* Reset watchdog. */
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outw(0x0008, DEFAULT_TCOBASE + 0x04); /* R/WC, clear TCO caused SMI. */
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outw(0x0002, DEFAULT_TCOBASE + 0x06); /* R/WC, clear second timeout. */
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/* Enable upper 128bytes of CMOS. */
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RCBA32(0x3400) = (1 << 2);
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/* Initialize power management initialization
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register early as it affects reboot behavior. */
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/* Bit 20 activates global reset of host and ME on cf9 writes of 0x6
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and 0xe (required if ME is disabled but present), bit 31 locks it.
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The other bits are 'must write'. */
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u8 reg8 = pci_read_config8(d31f0, 0xac);
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/* FIXME: It's a 8-bit variable!!! */
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reg8 |= (1 << 31) | (1 << 30) | (1 << 20) | (3 << 8);
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pci_write_config8(d31f0, 0xac, reg8);
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/* TODO: If RTC power failed, reset RTC state machine
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(set, then reset RTC 0x0b bit7) */
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/* TODO: Check power state bits in GEN_PMCON_2 (D31F0 0xa2)
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before they get cleared. */
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}
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