e21866781f
Currently, CIO gets enabled by the option Cio2Enable, but this duplicates the devicetree on/off options. Therefore, depend on the devicetree for the enablement of the CIO controller. All corresponding mainboards were checked if the devicetree configuration matches the Cio2Enable setting, and missing entries were added. Change-Id: I65e2cceb65add66e3cb3de7071b1a3cc967ab291 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44032 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
160 lines
5.0 KiB
Plaintext
160 lines
5.0 KiB
Plaintext
chip soc/intel/skylake
|
|
|
|
# IGD Displays
|
|
register "gfx" = "GMA_STATIC_DISPLAYS(0)"
|
|
|
|
register "gpu_pp_up_delay_ms" = "200"
|
|
register "gpu_pp_down_delay_ms" = " 50"
|
|
register "gpu_pp_cycle_delay_ms" = "500"
|
|
register "gpu_pp_backlight_on_delay_ms" = " 1"
|
|
register "gpu_pp_backlight_off_delay_ms" = "200"
|
|
|
|
register "gpu_pch_backlight_pwm_hz" = "1000"
|
|
|
|
# Enable deep Sx states
|
|
register "deep_s3_enable_ac" = "0"
|
|
register "deep_s3_enable_dc" = "0"
|
|
register "deep_s5_enable_ac" = "1"
|
|
register "deep_s5_enable_dc" = "1"
|
|
register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
|
|
|
|
# GPE configuration
|
|
# Note that GPE events called out in ASL code rely on this
|
|
# route. i.e. If this route changes then the affected GPE
|
|
# offset bits also need to be changed.
|
|
register "gpe0_dw0" = "GPP_B"
|
|
register "gpe0_dw1" = "GPP_D"
|
|
register "gpe0_dw2" = "GPP_E"
|
|
|
|
# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
|
|
register "gen1_dec" = "0x00fc0801"
|
|
register "gen2_dec" = "0x000c0201"
|
|
|
|
# Enable "Intel Speed Shift Technology"
|
|
register "speed_shift_enable" = "1"
|
|
|
|
# Enable DPTF
|
|
register "dptf_enable" = "1"
|
|
|
|
# FSP Configuration
|
|
register "ProbelessTrace" = "0"
|
|
register "SataSalpSupport" = "0"
|
|
register "SataMode" = "0"
|
|
register "SataPortsEnable[0]" = "0"
|
|
register "DspEnable" = "1"
|
|
register "IoBufferOwnership" = "3"
|
|
register "SsicPortEnable" = "0"
|
|
register "ScsEmmcHs400Enabled" = "1"
|
|
register "PttSwitch" = "0"
|
|
register "SkipExtGfxScan" = "1"
|
|
register "HeciEnabled" = "0"
|
|
register "SaGv" = "3"
|
|
register "PmConfigSlpS3MinAssert" = "2" # 50ms
|
|
register "PmConfigSlpS4MinAssert" = "4" # 4s
|
|
register "PmConfigSlpSusMinAssert" = "3" # 4s
|
|
register "PmConfigSlpAMinAssert" = "3" # 2s
|
|
register "PmTimerDisabled" = "1"
|
|
|
|
# Enable Root port 1
|
|
register "PcieRpEnable[0]" = "1"
|
|
# Enable CLKREQ#
|
|
register "PcieRpClkReqSupport[0]" = "1"
|
|
# RP 1 uses SRCCLKREQ1#
|
|
register "PcieRpClkReqNumber[0]" = "1"
|
|
|
|
# Must leave UART0 enabled or SD/eMMC will not work as PCI
|
|
register "SerialIoDevMode" = "{
|
|
[PchSerialIoIndexI2C0] = PchSerialIoPci,
|
|
[PchSerialIoIndexI2C1] = PchSerialIoPci,
|
|
[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
|
|
[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
|
|
[PchSerialIoIndexI2C4] = PchSerialIoPci,
|
|
[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
|
|
[PchSerialIoIndexSpi0] = PchSerialIoDisabled,
|
|
[PchSerialIoIndexSpi1] = PchSerialIoDisabled,
|
|
[PchSerialIoIndexUart0] = PchSerialIoPci,
|
|
[PchSerialIoIndexUart1] = PchSerialIoDisabled,
|
|
[PchSerialIoIndexUart2] = PchSerialIoSkipInit,
|
|
}"
|
|
|
|
# I2C4 is 1.8V
|
|
register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8"
|
|
|
|
# PL2 override 25W
|
|
register "power_limits_config" = "{
|
|
.tdp_pl2_override = 25,
|
|
}"
|
|
|
|
# Send an extra VR mailbox command for the PS4 exit issue
|
|
register "SendVrMbxCmd" = "2"
|
|
|
|
# Lock Down
|
|
register "common_soc_config" = "{
|
|
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
|
|
}"
|
|
|
|
device cpu_cluster 0 on
|
|
device lapic 0 on end
|
|
end
|
|
device domain 0 on
|
|
device pci 00.0 on end # Host Bridge
|
|
device pci 02.0 on end # Integrated Graphics Device
|
|
device pci 04.0 on end # SA thermal subsystem
|
|
device pci 14.0 on end # USB xHCI
|
|
device pci 14.1 off end # USB xDCI (OTG)
|
|
device pci 14.2 on end # Thermal Subsystem
|
|
device pci 14.3 off end # Camera
|
|
device pci 15.0 on end # I2C #0
|
|
device pci 15.1 on end # I2C #1
|
|
device pci 15.2 off end # I2C #2
|
|
device pci 15.3 off end # I2C #3
|
|
device pci 16.0 on end # Management Engine Interface 1
|
|
device pci 16.1 off end # Management Engine Interface 2
|
|
device pci 16.2 off end # Management Engine IDE-R
|
|
device pci 16.3 off end # Management Engine KT Redirection
|
|
device pci 16.4 off end # Management Engine Interface 3
|
|
device pci 17.0 off end # SATA
|
|
device pci 19.0 on end # UART #2
|
|
device pci 19.1 off end # I2C #5
|
|
device pci 19.2 on end # I2C #4
|
|
device pci 1c.0 on
|
|
chip drivers/intel/wifi
|
|
register "wake" = "GPE0_DW0_16"
|
|
device pci 00.0 on end
|
|
end
|
|
end # PCI Express Port 1
|
|
device pci 1c.1 off end # PCI Express Port 2
|
|
device pci 1c.2 off end # PCI Express Port 3
|
|
device pci 1c.3 off end # PCI Express Port 4
|
|
device pci 1c.4 off end # PCI Express Port 5
|
|
device pci 1c.5 off end # PCI Express Port 6
|
|
device pci 1c.6 off end # PCI Express Port 7
|
|
device pci 1c.7 off end # PCI Express Port 8
|
|
device pci 1d.0 off end # PCI Express Port 9
|
|
device pci 1d.1 off end # PCI Express Port 10
|
|
device pci 1d.2 off end # PCI Express Port 11
|
|
device pci 1d.3 off end # PCI Express Port 12
|
|
device pci 1e.0 on end # UART #0
|
|
device pci 1e.1 off end # UART #1
|
|
device pci 1e.2 off end # GSPI #0
|
|
device pci 1e.3 off end # GSPI #1
|
|
device pci 1e.4 on end # eMMC
|
|
device pci 1e.5 off end # SDIO
|
|
device pci 1e.6 off end # SDCard
|
|
device pci 1f.0 on
|
|
chip drivers/pc80/tpm
|
|
device pnp 0c31.0 on end
|
|
end
|
|
chip ec/google/chromeec
|
|
device pnp 0c09.0 on end
|
|
end
|
|
end # LPC Interface
|
|
device pci 1f.1 on end # P2SB
|
|
device pci 1f.2 on end # Power Management Controller
|
|
device pci 1f.3 on end # Intel HDA
|
|
device pci 1f.4 on end # SMBus
|
|
device pci 1f.5 on end # PCH SPI
|
|
device pci 1f.6 off end # GbE
|
|
end
|
|
end
|