e33c50d74c
AGESA and binaryPI set the whole CACHE_ROM_SIZE to WRPROT during the romstage and do not reference the CONFIG_XIP_ROM_SIZE symbol. Change-Id: I548b9c9066d825c2f03749353b9990b2efddfd9c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35825 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
73 lines
1.7 KiB
Plaintext
73 lines
1.7 KiB
Plaintext
#
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# This file is part of the coreboot project.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; version 2 of the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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config CPU_AMD_AGESA
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bool
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default y if CPU_AMD_AGESA_FAMILY12
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default y if CPU_AMD_AGESA_FAMILY14
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default y if CPU_AMD_AGESA_FAMILY15_TN
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default y if CPU_AMD_AGESA_FAMILY16_KB
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default n
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select ARCH_BOOTBLOCK_X86_32
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select ARCH_VERSTAGE_X86_32
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select ARCH_ROMSTAGE_X86_32
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select ARCH_RAMSTAGE_X86_32
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select DRIVERS_AMD_PI
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select TSC_SYNC_LFENCE
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select UDELAY_LAPIC
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select LAPIC_MONOTONIC_TIMER
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select SPI_FLASH if HAVE_ACPI_RESUME
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select SMM_ASEG
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select NO_FIXED_XIP_ROM_SIZE
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if CPU_AMD_AGESA
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config UDELAY_LAPIC_FIXED_FSB
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int
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default 200
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# TODO: Sync these with definitions in AGESA vendorcode.
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# DCACHE_RAM_BASE must equal BSP_STACK_BASE_ADDR.
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# DCACHE_RAM_SIZE must equal BSP_STACK_SIZE.
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config DCACHE_RAM_BASE
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hex
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default 0x30000
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config DCACHE_RAM_SIZE
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hex
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default 0x10000
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config ENABLE_MRC_CACHE
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bool "Use cached memory configuration"
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default n
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select SPI_FLASH
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help
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Try to restore memory training results
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from non-volatile memory.
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config S3_DATA_POS
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hex
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default 0xFFFF0000
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config S3_DATA_SIZE
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int
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default 32768
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endif # CPU_AMD_AGESA
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source src/cpu/amd/agesa/family12/Kconfig
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source src/cpu/amd/agesa/family14/Kconfig
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source src/cpu/amd/agesa/family15tn/Kconfig
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source src/cpu/amd/agesa/family16kb/Kconfig
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