e45d6bfd8a
A function to disable the PME# output was added. This is required to set up the SuperIO on the "HP Pro 3500 Series" mb. Change-Id: I94f023ba6eb24b5fb1c5e0b30eb65738f50a87eb Signed-off-by: Joel Linn <jl@conductive.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81589 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
180 lines
4.5 KiB
C
180 lines
4.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <arch/io.h>
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#include <device/pnp_ops.h>
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#include <device/pnp.h>
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#include <stdint.h>
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#include "ite.h"
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/* Global configuration registers. */
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#define ITE_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */
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#define ITE_CONFIG_REG_LDN 0x07 /* Logical Device Number. */
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#define ITE_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */
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#define ITE_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */
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#define ITE_CONFIG_REG_MFC 0x2a /* multi function pin */
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#define ITE_CONFIG_REG_WATCHDOG 0x72 /* watchdog config */
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#define ITE_CONFIG_REG_WDT_TIMEOUT_LSB 0x73 /* watchdog timeout (LSB) */
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#define ITE_CONFIG_REG_WDT_TIMEOUT_MSB 0x74 /* watchdog timeout (MSB) */
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#define ITE_CONFIG_REG_APC_PME_CTL1 0xf2 /* APC_PME Control 1 */
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#define ITE_CONFIG_REG_APC_PME_CTL2 0xf4 /* APC_PME Control 2 */
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/* Helper procedure */
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static void ite_sio_write(pnp_devfn_t dev, u8 reg, u8 value)
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{
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pnp_set_logical_device(dev);
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pnp_write_config(dev, reg, value);
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}
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/* Enable configuration */
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void pnp_enter_conf_state(pnp_devfn_t dev)
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{
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u16 port = dev >> 8;
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outb(0x87, port);
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outb(0x01, port);
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outb(0x55, port);
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outb((port == 0x4e) ? 0xaa : 0x55, port);
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}
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/* Disable configuration */
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void pnp_exit_conf_state(pnp_devfn_t dev)
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{
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ite_sio_write(dev, ITE_CONFIG_REG_CC, 0x02);
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}
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void ite_reg_write(pnp_devfn_t dev, u8 reg, u8 value)
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{
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pnp_enter_conf_state(dev);
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ite_sio_write(dev, reg, value);
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pnp_exit_conf_state(dev);
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}
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/*
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* in romstage.c
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* #define CLKIN_DEV PNP_DEV(0x2e, ITE_GPIO)
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* and pass: CLKIN_DEV
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* ITE_UART_CLK_PREDIVIDE_24
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* ITE_UART_CLK_PREDIVIDE_48 (default)
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*/
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void ite_conf_clkin(pnp_devfn_t dev, u8 predivide)
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{
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ite_reg_write(dev, ITE_CONFIG_REG_CLOCKSEL, (0x1 & predivide));
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}
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/* Bring up early serial debugging output before the RAM is initialized. */
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void ite_enable_serial(pnp_devfn_t dev, u16 iobase)
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{
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pnp_enter_conf_state(dev);
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pnp_set_logical_device(dev);
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pnp_set_enable(dev, 0);
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pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
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pnp_set_enable(dev, 1);
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pnp_exit_conf_state(dev);
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}
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/*
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*
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* LDN 7, reg 0x2a - needed for S3, or memory power will be cut off
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* this was documented only in IT8712F_V0.9.2!
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* Also documented in IT8728F_V0.4.2 and IT8772E_V0.4
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*
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* Enable 3VSBSW#. (For System Suspend-to-RAM)
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* 0: 3VSBSW# will be always inactive.
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* 1: 3VSBSW# enabled. It will be (NOT SUSB#) NAND SUSC#.
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*
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* in romstage.c
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* #define GPIO_DEV PNP_DEV(0x2e, ITE_GPIO)
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* and pass: GPIO_DEV
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*/
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void ite_set_3vsbsw(pnp_devfn_t dev, bool enable)
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{
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u8 tmp;
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pnp_enter_conf_state(dev);
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pnp_set_logical_device(dev);
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tmp = pnp_read_config(dev, ITE_CONFIG_REG_MFC);
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if (enable)
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tmp |= 0x80;
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else
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tmp &= ~0x80;
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pnp_write_config(dev, ITE_CONFIG_REG_MFC, tmp);
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pnp_exit_conf_state(dev);
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}
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/*
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*
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* LDN 7, reg 0x2a, bit 0 - delay PWRGD3 rising edge after 3VSBSW# rising edge
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* This can be needed for S3 resume.
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* Documented in IT8728F V0.4.2 but also applies to IT8720F where it is marked
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* as reserved.
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*
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* Delay PWRGD3 assertion after setting 3VSBSW#.
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* 0: There will be no extra delay before PWRGD3 is set.
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* 1: The delay after 3VSBSW# rising edge before PWRGD3 is set is increased.
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*
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* in romstage.c
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* #define GPIO_DEV PNP_DEV(0x2e, ITE_GPIO)
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* and pass: GPIO_DEV
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*/
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void ite_delay_pwrgd3(pnp_devfn_t dev)
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{
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u8 tmp;
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pnp_enter_conf_state(dev);
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pnp_set_logical_device(dev);
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tmp = pnp_read_config(dev, ITE_CONFIG_REG_MFC);
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tmp |= 0x01;
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pnp_write_config(dev, ITE_CONFIG_REG_MFC, tmp);
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pnp_exit_conf_state(dev);
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}
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/*
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* in romstage.c
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* #define GPIO_DEV PNP_DEV(0x2e, ITE_GPIO)
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* and pass: GPIO_DEV
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*/
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void ite_kill_watchdog(pnp_devfn_t dev)
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{
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pnp_enter_conf_state(dev);
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ite_sio_write(dev, ITE_CONFIG_REG_WATCHDOG, 0x00);
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ite_sio_write(dev, ITE_CONFIG_REG_WDT_TIMEOUT_LSB, 0x00);
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ite_sio_write(dev, ITE_CONFIG_REG_WDT_TIMEOUT_MSB, 0x00);
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pnp_exit_conf_state(dev);
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}
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/*
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* Disable PME# Output
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* pass EC_DEV
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*/
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void ite_disable_pme_out(pnp_devfn_t dev)
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{
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u8 tmp;
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pnp_enter_conf_state(dev);
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pnp_set_logical_device(dev);
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tmp = pnp_read_config(dev, ITE_CONFIG_REG_APC_PME_CTL1);
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tmp |= 0x40;
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pnp_write_config(dev, ITE_CONFIG_REG_APC_PME_CTL1, tmp);
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pnp_exit_conf_state(dev);
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}
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/*
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* Set AC resume to be up to the Southbridge
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* pass EC_DEV
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*/
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void ite_ac_resume_southbridge(pnp_devfn_t dev)
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{
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u8 tmp;
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pnp_enter_conf_state(dev);
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pnp_set_logical_device(dev);
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tmp = pnp_read_config(dev, ITE_CONFIG_REG_APC_PME_CTL2);
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/*
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* Set both
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* 6: Gate Extra PWRON# Pulse
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* 5: PSON# state when 3VSB switched to on
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*/
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tmp |= 0x60;
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pnp_write_config(dev, ITE_CONFIG_REG_APC_PME_CTL2, tmp);
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pnp_exit_conf_state(dev);
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}
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